Temperature aware refresh for DRAM performance improvement in 3D ICs

Guan, Menglong; Wang, Lei

doi:10.1109/isqed.2015.7085426

Cited by 7 publications

(11 citation statements)

References 9 publications

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“…Second, factors extrinsic to the DRAM device that depend on environmental or operating conditions. The most common extrinsic factors are aging [111,147], data values [74], and temperature [51]. Extrinsic factors can introduce significant variability in the error patterns.…”

Section: Enabling Eden With Error Modelsmentioning

confidence: 99%

Eden

Koppula

Orosa

Yağlıkçı

et al. 2019

Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture

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The effectiveness of deep neural networks (DNN) in vision, speech, and language processing has prompted a tremendous demand for energy-efficient high-performance DNN inference systems. Due to the increasing memory intensity of most DNN workloads, main memory can dominate the system's energy consumption and stall time. One effective way to reduce the energy consumption and increase the performance of DNN inference systems is by using approximate memory, which operates with reduced supply voltage and reduced access latency parameters that violate standard specifications. Using approximate memory reduces reliability, leading to higher bit error rates. Fortunately, neural networks have an intrinsic capacity to tolerate increased bit errors. This can enable energy-efficient and high-performance neural network inference using approximate DRAM devices.Based on this observation, we propose EDEN, the first general framework that reduces DNN energy consumption and DNN evaluation latency by using approximate DRAM devices, while strictly meeting a user-specified target DNN accuracy. EDEN relies on two key ideas: 1) retraining the DNN for a target approximate DRAM device to increase the DNN's error tolerance, and 2) efficient mapping of the error tolerance of each individual DNN data type to a corresponding approximate DRAM partition in a way that meets the user-specified DNN accuracy requirements.We evaluate EDEN on multi-core CPUs, GPUs, and DNN accelerators with error models obtained from real approximate DRAM devices. We show that EDEN's DNN retraining technique reliably improves the error resiliency of the DNN by an order of magnitude. For a target accuracy within 1% of the original DNN, our results show that EDEN enables 1) an average DRAM energy reduction of 21%, 37%, 31%, and 32% in CPU, GPU, and two different DNN accelerator architectures, respectively, across a variety of state-ofthe-art networks, and 2) an average (maximum) speedup of 8% (17%) and 2.7% (5.5%) in CPU and GPU architectures, respectively, when evaluating latency-bound neural networks.

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Section: Enabling Eden With Error Modelsmentioning

confidence: 99%

Eden

Koppula

Orosa

Yağlıkçı

et al. 2019

Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture

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“…Under the high temperature, conventional device-level management techniques may cause significant waste in energy and reduction in memory bandwidth [6]. As a result, fine-grained thermal-aware management methods for HMCs [6,7,16,26] have attracted a lot research interests. For example, authors of [6,16] proposed to tune the refresh rate at DRAM-row-level.…”

Section: Introductionmentioning

confidence: 99%

“…For several years, there is no free and publicly accessible HMC simulators. Therefore, the academia depends on simulators designed for 2D DRAMs (e.g., DRAMSim [20]) [7] to study the architecture and function of 3D DRAMs including HMCs. However, these simulators cannot accurately simulate the function of HMCs since HMCs have a special communication protocol with the host processor.…”

Section: Introductionmentioning

confidence: 99%

“…Despite the HMC simulator, current TM simulation frameworks for DRAMs are very inefficient since they are usually comprised of different tools/simulators [7,16,26]. Each tool performs a typical type of simulation (e.g., CasHMC for function simulation, DRAM-Power [4] for power simulation, HotSpot [9] for temperature simulation etc.…”

Section: Introductionmentioning

confidence: 99%

“…For example, in 2D DRAMs, the information of device-level power/temperature is enough since both the peak temperature and the thermal variance in 2D DRAMs are not large. In HMCs, however, if we still use the conventional framework to perform simulations of the fine-grained TM techniques [6,7,16,26], we will encounter great interface cost (since extremely large amount of intermediate data will be generated, reformatted, and transferred due to the large spatial/temporal sampling size).…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

HMCTherm

Yang

Zuzak

Srivastava

2018

Proceedings of the International Symposium on Memory Systems

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The hybrid memory cube (HMC) is a type of 3D stacked memory which is promising to overcome the "memory wall" problem of the conventional DRAM. However, the operating temperature of the HMC can be very high thus degrading the performance and even causing malfunction of the HMC. Therefore, fine-grained thermal-aware management (TM) techniques for HMCs are gaining increasing research interests. In order to design an efficient TM technique, a myriad of simulations should be performed at the early stage. However, current TM simulations for HMCs depend on complex frameworks which involve different tools. These conventional frameworks are very inefficient due to the heavy workload of generating and transferring intermediate data. In order to address this problem, we propose HMCTherm, a cycle-accurate simulator for the HMC with the integration of detailed power and thermal estimation. Compared to the conventional TM simulation framework, HMCTherm can significantly improve the simulation efficiency by avoiding redundant interface process. CCS CONCEPTS • Computing methodologies → Simulation tools; • Hardware → Temperature simulation and estimation; • Software and its engineering → Main memory;

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High Thermal Conductivity Insulators for Thermal Management in 3D Integrated Circuits

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2023

IEEE Electron Device Lett.

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Temperature aware refresh for DRAM performance improvement in 3D ICs

Cited by 7 publications

References 9 publications

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HMCTherm

High Thermal Conductivity Insulators for Thermal Management in 3D Integrated Circuits

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