Temperature-aware microarchitecture

Skadron, Kevin; Stan, Mircea R.; Huang, Wei; Velusamy, Sivakumar; Sankaranarayanan, Karthik; Tarjan, David

doi:10.1109/isca.2003.1206984

Cited by 77 publications

(180 citation statements)

References 10 publications

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“…HORNET integrates DSENT [55] and HOTSPOT 5.0 [56] to enable power and thermal analysis. In our experimental set-up, we operate HORNET in the networkonly mode.…”

Section: Simulation Detailsmentioning

confidence: 99%

Fault-Aware Load-Balancing Routing for 2D-Mesh and Torus On-Chip Network Topologies

Ren

Kinsy

Zheng

2016

IEEE Trans. Comput.

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Routing algorithm design for on-chip networks (OCNs) has become increasingly challenging due to high levels of integration and complexity of modern systems-on-chip (SoCs). The inherent unreliability of components, embedded oversized IP blocks, and fine-grained voltage-frequency islands (VFIs) management among others, raise several challenges in OCNs: (a) network topologies become irregular or asymmetric making circular route dependencies that lead to deadlock hard to detect; and (b) routing algorithms that lack strong load-balancing properties often saturate prematurely. In order to address the aforementioned deadlock and load-balancing problems, we propose the traffic balancing oblivious routing (TBOR) algorithm. It is a 2-phase routing algorithm consisting of: (1) construction of the weighted acyclic channel dependency graph (CDG) for the OCN to efficiently maximize available resource utilization; and (2) channel ordering across turn models to keep the underlying CDG cycle-free to guarantee deadlock-freedom using one or more turn-models. Channel bandwidth utilization and traffic balancing are achieved through static virtual channel allocation according to residual bandwidth of healthy links. In addition, we introduce in this work two schemes of different granularity of fault detection and analysis while guaranteeing in-order packet delivery by assigning a unique path to each flow. Extensive experiments demonstrate the proposed routing methodology outperforms previous algorithms.

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“…HORNET integrates DSENT [55] and HOTSPOT 5.0 [56] to enable power and thermal analysis. In our experimental set-up, we operate HORNET in the networkonly mode.…”

Section: Simulation Detailsmentioning

confidence: 99%

Fault-Aware Load-Balancing Routing for 2D-Mesh and Torus On-Chip Network Topologies

Ren

Kinsy

Zheng

2016

IEEE Trans. Comput.

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“…Traditionally, MPSoC architectures [1] have been driven by features that improve performance, but constrained by power and thermal budgets [13]. Power-aware [14], thermal-aware [5], and reliability-aware [15] over the last decade. However, a computing framework that addresses and assures the dependability of the information processing (i.e., the cyber aspects such as integrity, correctness, accuracy, timing, reliability and security) while simultaneously addressing the physical manifestations (in performance, power, thermal, aging, wear-out, material degradation, and reliability/dependability) of the information processing on the underlying computing platform, specifically SoC, has been missing.…”

Section: Related Work and Motivationmentioning

confidence: 99%

“…on-chip peak temperature [5]), MPSoCs can be considered as a controlled network computing system (in a very limited or specific way) in the spirit of the definition † This work was partially supported by the NSF Variability Expedition award CCF-1029783. Also, the support of the FPGA prototyping boards from Xilinx Inc is acknowledged.…”

Section: Introductionsmentioning

confidence: 99%

FPGA emulation and prototyping of a cyberphysical-system-on-chip (CPSoC)

Sarma

Dutt

2014

2014 25nd IEEE International Symposium on Rapid System Prototyping

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Cyber-Physical Systems-on-Chip (CPSoC) are a new class of sensor-and actuator-rich multiprocessor system-onchips (MPSoCs) whose operations are monitored, coordinated, and controlled using a computing-communication-control (C3) centric core with additional on-chip and cross-layer sensing and actuation capabilities that enable self-awareness within the observe-decide-act (ODA) paradigm. In order to build, evaluate, and illustrate the effectiveness of various features of this new MPSoC paradigm in a fast and cost effective way, a rapid prototyping and emulation platform along with the tool chains is absolutely necessary. In this paper, we present a design library and an FPGA emulation and prototyping platform to build and investigate self-aware adaptive computing using CPSoC paradigm. Our example implementation of CPSoC prototyping using Xilinx FPGAs includes ring-oscillator (RO) based multipurpose sensors integrated with a sensor network-on-chip (sNoC) which in turn is interfaced either to a bus based shared memory architecture or to a communication and computation networkon-chip (cNoC) distributed fabric supporting several actuation mechanism in the software and hardware stack. We also briefly discuss few applications of the CPSoC design library and the platform.

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“…To analysis the impact of the proposed inter-layer bus scheme on the chip temperature of a 36-node on-chip network (3×3×4), we use the Hotspot simulator [24] using the complete layout of the entire chip along with the power numbers for each component. We use the average power consumption, including leakage, area and the floorplan from the SPARC Niagara design (90nm) [25] for the processors while power numbers for the cache memories are obtained from CACTI.…”

Section: Thermal Analysismentioning

confidence: 99%

HIBS — Novel inter-layer bus structure for stacked architectures

Daneshtalab

Ebrahimi

Plosila

2012

2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International

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Three-dimensional integrated circuit (3D IC) technology has emerged as a viable candidate to overcome the interconnections scaling and integration complexity in next generation digital system designs. In addition, combining the benefits of 3D ICs and Networks-on-Chip (NoCs) schemes provides a significant performance gain for 3D architectures. In recent years, through-silicon-via (TSV), employed for interlayer connectivity (vertical channel), has attracted a lot of interest since it enables faster and more power efficient interlayer communication across multiple stacked layers. The busbased organization, a hybrid between packet-switched network and a bus, is a dominant architecture for utilizing TSVs as inter-layer communication channel in 3D architectures. In this paper, we propose a novel bus structure for inter-layer communication to improve the performance by reducing the delay and complexity of traditional bus arbitration.

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Temperature-aware microarchitecture

Cited by 77 publications

References 10 publications

Fault-Aware Load-Balancing Routing for 2D-Mesh and Torus On-Chip Network Topologies

Fault-Aware Load-Balancing Routing for 2D-Mesh and Torus On-Chip Network Topologies

FPGA emulation and prototyping of a cyberphysical-system-on-chip (CPSoC)

HIBS — Novel inter-layer bus structure for stacked architectures

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Temperature-aware microarchitecture

Cited by 77 publications

References 10 publications

Fault-Aware Load-Balancing Routing for 2D-Mesh and Torus On-Chip Network Topologies

Fault-Aware Load-Balancing Routing for 2D-Mesh and Torus On-Chip Network Topologies

FPGA emulation and prototyping of a cyberphysical-system-on-chip (CPSoC)

HIBS &#x2014; Novel inter-layer bus structure for stacked architectures

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Product

Resources

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HIBS — Novel inter-layer bus structure for stacked architectures