HIBS — Novel inter-layer bus structure for stacked architectures

Abstract

Three-dimensional integrated circuit (3D IC) technology has emerged as a viable candidate to overcome the interconnections scaling and integration complexity in next generation digital system designs. In addition, combining the benefits of 3D ICs and Networks-on-Chip (NoCs) schemes provides a significant performance gain for 3D architectures. In recent years, through-silicon-via (TSV), employed for interlayer connectivity (vertical channel), has attracted a lot of interest since it enables faster and more power efficient interlayer communication across multiple stacked layers. The busbased organization, a hybrid between packet-switched network and a bus, is a dominant architecture for utilizing TSVs as inter-layer communication channel in 3D architectures. In this paper, we propose a novel bus structure for inter-layer communication to improve the performance by reducing the delay and complexity of traditional bus arbitration.

Efficient 3-D Bus Architectures for Inductive-Coupling ThruChip Interfaces

“…To take advantage of this benefit, bus-based 3-D NoCs have been studied in TSV-based 3-D ICs [20]- [22]. In such bus-based 3-D NoCs, vertical buses are used for interchip communication, while packet-switched networks are used for intrachip communication.…”

“…High-performance Inter-layer Bus Structure [22] has a pipelined bus structure that allows simultaneous data transfers from more than two sources. Since additional control lines can be implemented with a relatively low cost with TSVs, an interchip hardware arbiter can be implemented for a vertical bus.…”

Energy reduction in 3D NoCs through communication optimization

“…Ebrahimi et al [10] discuss how 3D architectures with a large number of TSVs can be built using mesh-based topologies. In [11], authors not only reduce the communication delay, but also improve the thermal behavior in a 3D NoC architecture. Coskun et al [12] propose a dynamic thermally-aware job scheduling technique for 3D architectures to reduce the thermal problems at very low performance cost.…”