Temperature and on-chip crosstalk measurement using ring oscillators in FPGA

Gag, Martin; Wegner, Tim; Waschki, Ansgar; Timmermann, Dirk

doi:10.1109/ddecs.2012.6219057

Cited by 23 publications

(14 citation statements)

References 6 publications

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“…The study found that other logic existed inside the LAB of RO-14, leading to heavier routings. Hence, the RO exposed noises more than others [23,24,41].…”

Section: Metric Improvementmentioning

confidence: 94%

Routing Density Analysis of Area-Efficient Ring Oscillator Physically Unclonable Functions

et al. 2021

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The research into ring oscillator physically unclonable functions (RO-PUF) continues to expand due to its simple structure, ease of generating responses, and its promises of primitive security. However, a substantial study has yet to be carried out in developing designs of the FPGA-based RO-PUF, which effectively balances performance and area efficiency. This work proposes a modified RO-PUF where the ring oscillators are connected directly to the counters. The proposed RO-PUF requires fewer RO than the conventional structure since this work utilizes the direct pulse count method. This work aims to seek the ideal routing density of ROs to improve uniqueness. For this purpose, five logic arrangements of a wide range of routing densities of ROs were tested. Upon implementation onto the FPGA chip, the routing density of ROs are varied significantly in terms of wire utilization (higher than 25%) and routing hotspots (higher than 80%). The best uniqueness attained was 52.71%, while the highest reliability was 99.51%. This study improves the uniqueness by 2% subsequent to the application of scenarios to consider ROs with a narrow range of routing density. The best range of wire utilization and routing hotspots of individual RO in this work is 3–5% and 20–50%, respectively. The performance metrics (uniqueness and reliability) of the proposed RO-PUF are much better than existing works using a similar FPGA platform (Altera), and it is as good as the recent RO-PUFs realized on Xilinx. Additionally, this work estimates the minimum runtimes to reduce error and response bit-flip of RO-PUF.

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“…The study found that other logic existed inside the LAB of RO-14, leading to heavier routings. Hence, the RO exposed noises more than others [23,24,41].…”

Section: Metric Improvementmentioning

confidence: 94%

Routing Density Analysis of Area-Efficient Ring Oscillator Physically Unclonable Functions

et al. 2021

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“…In our work, we are trying to extend this approach from CPLD to FPGA and VHDL to Verilog. Method of time to digital conversion to measure the coupling capacitances effect in interconnection structure of FPGAs is demonstrated [2]. Input and Output Power is a part of dynamic power.…”

Section: Related Workmentioning

confidence: 99%

Output load capacitance based low power implementation of UART on FPGA

Singh

Pandey

Kumar

et al. 2014

2014 International Conference on Computer Communication and Informatics

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Core dynamic power is independent of output load capacitance. IO power and static power is dependent on output load capacitance. In this work, we achieved 99.72% reduction in IOs power consumption of Universal Asynchronous Receiver Transmitter (UART) if we scale down output load from 10,000pf to 5pF in IOB setting of FPGA. Universal Asynchronous Receiver and Transmitter are a transceiver circuits that transmit/receive data between parallel and serial forms and vice versa. Design state of our design is high because no black box found. Bit width is high because 57.6% of primitives in RTL net list represent 1-bit logic. Here, IO power consumption is 17,226mW on 10,000pF output load which significantly reduce to 47mW on 5pF output load. Along with reduction in IOs power, we also observed 24.5% reduction in static power consumption from 1322mW on 10,000pF output load to 1004mW on 5pF output load. In our implementation on FPGA, we take Virtex-6 family, XC6VLX75T device, FF484 package, -1 speed grade, XST synthesis tool, ISim simulator, and Verilog as preferred HDL language.

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“…Prior work has shown that the values carried by long wires affect the delays of their adjacent long wires in a way which can be measured on-chip by estimating the frequency of ring oscillators (ROs). The victim wire may be in sync with the RO for crosstalk measurement [6], or completely independent for covert-and sidechannel attacks. The main insight behind these attacks is that when a long wire carries a 1, adjacent long wires become slightly faster compared to when the same wire is carrying a 0.…”

Section: Long-wire Leakagementioning

confidence: 99%