Technology Scaling and Device Design for 350 GHz RF Performance in a 45nm Bulk CMOS Process

Li, Hongmei; Jagannathan, B.; Wang, Jing; Su, Tai-Chi; Sweeney, S.; Pekarik, John J.; Shi, Yaning; Greenberg, D.; Jin, Zhiyang; Groves, R.; Wagner, L.; Csutak, S.M.

doi:10.1109/vlsit.2007.4339725

Cited by 37 publications

(14 citation statements)

References 2 publications

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“…These performances are benchmarked against other CMOS 65&45 nm technology nodes into the next section. [10][11] and 60 GHz [11]. It turns out that NFmin at 40 GHz and at 60 GHz for the technology are in line with previous results.…”

Section: Noise Performancessupporting

confidence: 86%

“…Surprisingly, despite better f MAX for the technology compared to [11], the minimum noise figure is not significantly improved; this is attributed to the quite high gate resistance value (as already mentioned in Section II.B). On the other hand, the G ass is better compared to [10] and [11]. These results confirm attractive potentialities of 45 nm technology for low noise applications in the mmW range.…”

Section: Noise Performancessupporting

confidence: 66%

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Small signal and HF noise performance of 45 nm CMOS technology in mmW range

Poulain

Waldhoff

Gloria

et al. 2011

2011 IEEE Radio Frequency Integrated Circuits Symposium

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The development of applications in millimeter wave range (mmW) during the last decade is strongly related to continuous progress of Si Technology, which kept on evolving through aggressive transistor gate length down-scaling. In this context, this paper aims to present DC, small signal and noise performance up mmW range of recently developed 45-nm bulk CMOS Technology. For this purpose, S parameters were measured up to 67 GHz, a high frequency (HF) noise model was extracted in 6-40 GHz frequency range, and its accuracy verified through a comparison with the noise figure measured in W band with a 50 Ω impedance set at the transistor. The technology offers f T , f MAX respectively of 200 and 300 GHz in line with up-to-date published results for a 45 nm CMOS Technology. At the meantime, a minimum noise figure of 4.5 dB at 94 GHz is demonstrated (verified through W band noise measurements).Index Terms -Millimeter wave measurement, CMOS 45nm, Sparameters, small signal model, noise model.

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Section: Noise Performancessupporting

confidence: 86%

Section: Noise Performancessupporting

confidence: 66%

Small signal and HF noise performance of 45 nm CMOS technology in mmW range

Poulain

Waldhoff

Gloria

et al. 2011

2011 IEEE Radio Frequency Integrated Circuits Symposium

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“…The advanced nanoscale CMOS technologies have been widely used to build these circuit blocks thanks to several advantages: low-cost, low power consumption, compact layout size, and high-level integration. Besides, with the scaling-down of CMOS technologies into deep submicron range (e.g., 65, 40, and 28 nm), these siliconbased technologies become promising to realize circuits for 60-GHz applications, thanks to the performance enhancement of transistors in terms of transition frequency f t and maximum oscillation frequency f max , (e.g., f t /f max 5 280/350 GHz in a 40 nm CMOS process [9]). However, the continuing scaling-down of CMOS technology nodes makes the design of millimeter-wave PA much more challenging, due to the lower breakdown voltage which is in the order of 1 V for advanced CMOS technologies and more stringent electromigration design rules.…”

Section: Introductionmentioning

confidence: 99%

Millimeter-wave CMOS power amplifier using slow-wave transmission lines

Tang

Pistono

Fournier

et al. 2015

2015 Asia-Pacific Microwave Conference (APMC)

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A three-stage 60-GHz power amplifier (PA) has been implemented in a 65 nm Complementary Metal Oxide Semiconductor (CMOS) technology. High-quality-factor slowwave coplanar waveguides (S-CPW) were used for input, output and inter-stage matching networks to improve the performance. Being biased for Class-A operation, the PA exhibits a measured power gain G of 18.3 dB at the working frequency, with a 3-dB bandwidth of 8.5 GHz. The measured 1-dB output compression point (OCP 1dB ) and the maximum saturated output power P sat are 12 dBm and 14.2 dBm, respectively, with a DC power consumption of 156 mW under 1.2 V voltage supply. The measured peak power added efficiency PAE is 16%. The die area is 0.52 mm 2 (875 3 600 lm 2 ) including all the pads, whereas the effective area is only 0.24 mm

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“…Deep sub-micron CMOS and state-of-the-art SiGe HBT technologies now achieve RF figures-of-merit (FoM) for f T and f max in the range of half a terahertz [1], [2]. While this is clearly very promising for the development of ICs that can revolutionize many applications in the millimeter-wave to submillimeter-wave frequencies (e.g., 30 GHz to 300 GHz), the intrinsic device speed by itself is by no means a sufficient metric to determine the RF performance of a technology at the circuit level.…”

Section: Introductionmentioning

confidence: 99%

An investigation of f<inf>T</inf> and f<inf>max</inf> degradation due to device interconnects in 0.5 THz SiGe HBT technology

Ulusoy

Schmid

Zeinolabedinzadeh

et al. 2014

2014 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)

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In this paper, the authors investigate the impact of device interconnect parasitics on the two most commonlyaccepted RF small-signal figures-of-merit, the transit frequency (fT) and the maximum frequency of oscillation (fmax) in stateof-the-art SiGe HBT technology. Simulations and measurement results are provided as a guideline to design an optimum device interconnect scheme to achieve a high fmax. Test structures were characterized with de-embedding structures providing reference planes at the device level and at the top-metal level. Measurements show an fmax of 450 GHz at the device level and at the topmetal level a degradation of only 4% to 430 GHz. These results demonstrate a significant advantage of the SiGe HBT technology compared to ultra-scaled CMOS technology at device speeds approaching a terahertz, and to the best of the authors' knowledge, demonstrate the highest fmax reported at the top-metal level in any state-of-the-art silicon technology.

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Technology Scaling and Device Design for 350 GHz RF Performance in a 45nm Bulk CMOS Process

Cited by 37 publications

References 2 publications

Small signal and HF noise performance of 45 nm CMOS technology in mmW range

Small signal and HF noise performance of 45 nm CMOS technology in mmW range

Millimeter-wave CMOS power amplifier using slow-wave transmission lines

An investigation of f<inf>T</inf> and f<inf>max</inf> degradation due to device interconnects in 0.5 THz SiGe HBT technology

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