Technology of GaN-Based Large Area CAVETs With Co-Integrated HEMTs

Döring, Philipp; Driad, R.; Reiner, Richard; Waltereit, Patrick; Mikulla, M.; Ambacher, O.

doi:10.1109/ted.2021.3109840

Cited by 11 publications

(4 citation statements)

References 25 publications

(31 reference statements)

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“…A combination of lateral and vertical structure with key focus of integration and at the same time higher performance combines the advantages of both technologies. A suitable structure for the combination offers the current aperture vertical electron transistor (CAVET) [97], shown in Fig. 18.…”

Section: ) Combination Of Lateral and Vertical Technologiesmentioning

confidence: 99%

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Building Blocks for GaN Power Integration

Basler¹,

Reiner

Moench

et al. 2021

IEEE Access

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GaN technology is on the advance for the use in power ICs thanks to space-saving integrated circuit components and the increasing number of integrated devices. This work experimentally investigates a number of key building blocks for GaN power integration. First, an overview of the active and passives devices of the technology is given with focus on area-efficient layouts for power transistors and limitations of on-chip capacitors and inductors with comparison to other IC technologies. Digital and analog basic circuits as part of device libraries are examined and optimized with regard to area-efficiency. The NOT gates have active areas as low as 56.7 µm 2 and max. static currents of 0.12 mA with high noise margins. Further digital gates are presented. For the analog circuits, differential amplifiers and voltage reference concepts are presented and compared. Finally, GaN power integration is discussed, and integration levels are defined and described. The GaN technology is compared with other IC technologies, and future challenges and perspectives are shown. GaN power integration based on building blocks aims to exploit the full potential of the lateral GaN technology in order to compete with Si-based IC technologies in the future.INDEX TERMS Gallium nitride, integrated circuit technology, power integrated circuits, logic circuits, analog circuits

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Section: ) Combination Of Lateral and Vertical Technologiesmentioning

confidence: 99%

“…a VIA. This well allows to avoid static and dynamic influences of the drain potential to the lateral HEMTs [97]. Other approaches are also conceivable, such as a GaN/SiC hybrid FET based on a GaN-on-SiC epitaxial growth to combine the advantages of both material systems [102].…”

Section: ) Combination Of Lateral and Vertical Technologiesmentioning

confidence: 99%

Building Blocks for GaN Power Integration

Basler¹,

Reiner

Moench

et al. 2021

IEEE Access

Self Cite

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“…Gallium nitride (GaN) has been widely researched as the next generation of efficient power electronic devices because of its wide band gap (E g = 3.4 eV), high critical electric field, fast switching speed, and high Baliga figure of merit. In the past few years, the GaN's material properties and the advantages of vertical devices, including vertical Schottky barrier diodes [1][2][3][4][5][6][7][8], PN diodes [9][10][11][12][13][14][15][16][17][18], JBS diodes [19], and transistors [20][21][22][23][24][25][26][27][28][29], such as metal-oxide-semiconductor field-effect transistors (MOSFETs), fin field-effect transistors, and current aperture vertical electron transistors, have been combined to achieve better performance. * Author to whom any correspondence should be addressed.…”

Section: Introductionmentioning

confidence: 99%

Study of drain-induced channel effects in vertical GaN junction field-effect transistors

Chen,

Yue,

Zhu

et al. 2024

Semicond. Sci. Technol.

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In this work, a normally-off vertical gallium nitride (GaN) junction field-effect transistor (JFET) was demonstrated. The device shows a current on/off ratio of 3.6×10^10, a threshold voltage (VTH) of 1.64 V and a specific on-resistance (RON,SP) of 1.87 mΩ·cm^2. Drain induced channel effects were proposed to explain the change of gate current at different drain voltages. Drain current decline in the output characteristics and the reverse turn-on between drain and source can be explained by the effects. Technology computer aided design (TCAD) was used to simulate the change of the depletion region and confirm the explanation. Detailed analyses of the channel effects provide a reference for the design of new structures. The characteristics at different temperatures were demonstrated to show the stability of threshold voltage and specific on-resistance, which indicates the great potential of application in switching power circuit of vertical GaN JFETs.

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“…Moreover, the peak electric field (Efield) of a vertical GaN device is far from the surface, and is less affected by traps or defects in the surface, thus achieving better reliability. Several vertical GaN devices have been reported, such as the current aperture vertical electronic transistor (CAVET), [7][8][9] the metal-oxide-semiconductor field-effect transistor (MOSFET) with a trench gate [10][11][12] and GaN vertical fin transistors. [13][14][15] In practical power electronics applications, a freewheeling diode (FWD) is necessary to provide a reverse current flow path.…”

Section: Introductionmentioning

confidence: 99%

High-performance vertical GaN field-effect transistor with an integrated self-adapted channel diode for reverse conduction

et al. 2023

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In this work, a vertical GaN FET with an Integrated self-adapted Channel diode (CD-FET) is proposed to improve its reverse conduction performance. It features a channel diode (CD) formed between a trench source on the insulator and a P-type barrier layer (PBL), together with a P-shield layer under the trench gate. At the forward conduction, the channel diode is pinched-off due to depletion effects caused by both the PBL and the MIS structure from the trench source, without influence on on-state characteristic of the CD-FET. At the reverse conduction, the depletion regions narrow, and thus the channel diode turns on to achieve a very low turn-on voltage (V F) and prevents the inherent body diode from turning on. Meanwhile, the PBL and P-shield layer could modulate the E-field distribution to improve the off-state breakdown voltage (BV). Moreover, the P-shield not only shields the gate from a high electric field , but also transforms part of C GD to C GS so as to significantly reduce the gate charge (Q GD), leading to a low switching loss (E switch). Consequently, the proposed CD-FET achieves a low V F = 1.65 V, high BV = 1446 V, and the V F, Q GD and E switch of the CD-FET are decreased by 49%, 55%, and 80%, respectively, compared with those of the Conventional MOSFET.

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Technology of GaN-Based Large Area CAVETs With Co-Integrated HEMTs

Cited by 11 publications

References 25 publications

Building Blocks for GaN Power Integration

Building Blocks for GaN Power Integration

Study of drain-induced channel effects in vertical GaN junction field-effect transistors

High-performance vertical GaN field-effect transistor with an integrated self-adapted channel diode for reverse conduction

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