Technology mapping flow for emerging reconfigurable silicon nanowire transistors

Rai, Shubham; Raitza, Michael; Kumar, Akash

doi:10.23919/date.2018.8342110

Cited by 19 publications

(8 citation statements)

References 11 publications

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“…In this brief example of a function-level reconfigurable logic circuit, the number of gates is only increased by 1 compared to the standalone circuit, but the number of realized functions is doubled. Compared to the baseline synthesis flow of ABC that utilizes reconfigurable gates as part of library [32], the proposed circuit can better leverage the potential of reconfigurable gates. An example of multi-output benchmark 'lion' is provided in Fig.…”

Section: A Proposed Concept Of Reconfigurable Logic Circuitmentioning

confidence: 99%

“…Another proposed scheme is technology mapping based on mature and scalable graph methods that aim to leverage RLGs. This scheme is area competitive and uses RLGs as compact logic gates by regarding the RLGs' control (i.e., switch) signals as inputs [13,[29][30][31][32]. Such RLGs are added to the library and deployed in the circuit during logic mapping.…”

Section: Introductionmentioning

confidence: 99%

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Towards Area Efficient Logic Circuit: Exploring Potential of Reconfigurable Gate by Generic Exact Synthesis

Shang

Naeemi

Pan

2023

IEEE Open J. Comput. Soc.

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In this paper, we propose a generic design methodology to achieve area-efficient reconfigurable logic circuits by using exact synthesis based on Boolean satisfiability (SAT) solver. The proposed methodology better leverages the high representation ability of emerging reconfigurable logic gates (RLGs) to achieve reconfigurable circuits with fewer gates. In addition, we propose a fence-based acceleration method to provide >10× speed up for the synthesis without an observable loss of optimality. Furthermore, four sets of RLGs are developed based on a recently proposed valley-spin device as a case study to demonstrate the advantage of the proposed circuit. Simulations have been performed to analyze the impact of the fence searching algorithm and combination of operators. Based on disjointsupport decomposable (DSD) benchmarks, up to 38% and 73% reductions are observed in the area and energy-delay-area product (EDAP), respectively, compared to CMOS counterparts. Compared to the two existing synthesis methods, the proposed scheme provides 40% and 26.3% reduction in EDAP based on MCNC benchmark.

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Section: A Proposed Concept Of Reconfigurable Logic Circuitmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Towards Area Efficient Logic Circuit: Exploring Potential of Reconfigurable Gate by Generic Exact Synthesis

Shang

Naeemi

Pan

2023

IEEE Open J. Comput. Soc.

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“…At the logical abstraction, the runtime-reconfigurable properties offered by RFETs can be used to build logic gates with extended functionality [61,52,57,62,63]. These logic gates can be configured to deliver different logic functionalities on application of an external potential.…”

Section: B Polymorphic Logic Gates and Logic Lockingmentioning

confidence: 99%

Vertical IP Protection of the Next-Generation Devices: Quo Vadis?

Rai

Garg

Pilato

et al. 2021

2021 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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With the advent of 5G and IoT applications, there is a greater thrust in terms of hardware security due to imminent risks caused by high amount of intercommunication between various subsystems. Security gaps in integrated circuits, thus represent high risks for both-the manufacturers and the users of electronic systems. Particularly in the domain of Intellectual Property (IP) protection, there is an urgent need to devise security measures at all levels of abstraction so that we can be one step ahead of any kind of adversarial attacks. This work presents IP protection measures from multiple perspectives-from systemlevel down to device-level security measures, from discussing various attack methods such as reverse engineering and hardware Trojan insertions to proposing new-age protection measures such as multi-valued logic locking and secure information flow tracking. This special session will give a holistic overview at the current state-of-the-art measures and how well we are prepared for the next generation circuits and systems.1 Not requiring any changes to the EDA flows.

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“…Changing the polarity of one of the gate terminals for RFETs leads to runtime-reconfigurability. This can be well abstracted in mathematics using a Higher Order function (HOF) as described in the following equation [42]: f (x, y, z, w) = д(x, y, z), when w = 0 = h(x, y, z), when w = 1…”

Section: Higher Order Functionsmentioning

confidence: 99%

“…Apart from logic synthesis flow, a crucial aspect is to devise physical synthesis flows which can evaluate the promise which newer nanotechnologies hold, on larger benchmarks. An early evaluation has been carried out in [42] for silicon nanowire reconfigurable FETs based circuits. Such evaluation is necessary to extrapolate how a lab-level research technology competes with CMOS for larger and more complex circuits.…”

Section: Introductionmentioning

confidence: 99%

Emerging reconfigurable nanotechnologies

Rail

Srinivasa

Cadareanu

et al. 2018

Proceedings of the International Conference on Computer-Aided Design

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Several emerging reconfigurable technologies have been explored in recent years offering device level runtime reconfigurability. These technologies offer the freedom to choose between p-and n-type functionality from a single transistor. In order to optimally utilize the feature-sets of these technologies, circuit designs and storage elements require novel design to complement the existing and future electronic requirements. An important aspect to sustain such endeavors is to supplement the existing design flow from the device level to the circuit level. This should be backed by a thorough evaluation so as to ascertain the feasibility of such explorations. Additionally, since these technologies offer runtime reconfigurability and often encapsulate more than one functions, hardware security features like polymorphic logic gates and on-chip key storage come naturally cheap with circuits based on these reconfigurable technologies. This paper presents innovative approaches devised for circuit designs harnessing the reconfigurable features of these nanotechnologies. New circuit design paradigms based on these nano devices will be discussed to brainstorm on exciting avenues for novel computing elements.

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Technology mapping flow for emerging reconfigurable silicon nanowire transistors

Cited by 19 publications

References 11 publications

Towards Area Efficient Logic Circuit: Exploring Potential of Reconfigurable Gate by Generic Exact Synthesis

Towards Area Efficient Logic Circuit: Exploring Potential of Reconfigurable Gate by Generic Exact Synthesis

Vertical IP Protection of the Next-Generation Devices: Quo Vadis?

Emerging reconfigurable nanotechnologies

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