Technology assessment of silicon interposers for manycore SoCs: Active, passive, or optical?

Thonnart, Yvain; Zid, Mounir

doi:10.1109/nocs.2014.7008777

Cited by 10 publications

(5 citation statements)

References 4 publications

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“…On-chip inductor is an important passive device in radiofrequency integrated circuits (RFICs) [1]. 3-D packaging technology using through-silicon vias (TSVs) initiates the realization of passive components including on-chip inductor, capacitor, filters, and so on [2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19]. Compared with a conventional 2-D inductor, a TSV-based 3-D inductor has advantages of high inductance density and less form factor [20][21][22][23][24].…”

Section: Introductionmentioning

confidence: 99%

Analytical models of AC inductance and quality factor for TSV-based inductor

Yin

Wang

2021

IEICE Electron. Express

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Aimed at the emerging on-chip three-dimensional throughsilicon vias (TSVs)-based inductor, the formula for the DC inductance is proposed. And then, based on this formula and the equivalent circuit model analytical models of AC inductance and quality factor are proposed considering frequency effect. Finally, the TSV-based inductors are fabricated and measured. It is shown that the reported results match very well with each other.

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Section: Introductionmentioning

confidence: 99%

Analytical models of AC inductance and quality factor for TSV-based inductor

Yin

Wang

2021

IEICE Electron. Express

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“…While passive interposers have been developed and used in production since a few years, demonstrations of active CMOS interposers are just emerging [2]. As silicon photonics technology is now reaching maturity with a broad palette of optimized devices [3], and with several groups that have pushed the Network-on-Chip paradigm to new optical flavors, leading to optical NoC (ONoC) architectures and systems, we had investigated the breakeven point of passive, active and optical interposer technologies for large-scale manycore systems [4]. We will present the motivations (Section II), technology constraints (Section III) and design choices (Section IV) that led us to the definition of the POPSTAR ONoC topology and E/O chiplet for a robust modular architecture, which will be detailed in Section V.…”

Section: Introductionmentioning

confidence: 99%

POPSTAR: a Robust Modular Optical NoC Architecture for Chiplet-based 3D Integrated Systems

Thonnart

Bernabé

Charbonnier

et al. 2020

2020 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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Silicon photonics technology is now gaining maturity with increasing levels of design complexity from devices to large photonic integrated circuits. Close integration of control electronics with 3D assembly of photonics and CMOS opens the way to high-performance computing architectures partitioned in chiplets connected by optical NoC on silicon photonic interposers. In this paper, we give an overview of our works on optical links and NoC for manycore systems, from low-level control of photonic devices to high-level system optimization of the optical communications. We detail the POPSTAR optical NoC topology and architecture (Processors On Photonic Silicon interposer Terascale ARchitecture) with electro-optical interface chiplets, the corresponding nested spiral topology for single-writer multiplereader links and the associated control electronics, in charge of high-speed drivers, thermal stabilization and handling of the protocol stack, from data integrity to flow-control, routing and arbitration of the optical communications. The strengths and opportunities for this architecture will be discussed, with a shift in system & implementation constraints with respect to previous optical NoC proposals, and new challenges to be addressed.

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“…The active interposer is more suitable for large integration. Passive and active interposers are the same in logical behavior, but their physical activity is different …”

Section: Introductionmentioning

confidence: 99%

An expandable topology with low wiring congestion for silicon interposer‐based network‐on‐chip systems

Dadashi

Reshadi

Reza

et al. 2019

Trans Emerging Tel Tech

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In 2.5D stacking technology, multiple chips have stacked side-by-side on a silicon interposer layer. The network-on-chip in the central processing unit (CPU) layer makes it possible to connect processing cores to each other. The interposer layer prepares the connection between the CPU cores and other chips such as memory chip. The memory chip usually contains several segments stacked vertically. The network-on-chip can be extended to the interposer layer to make use of unused routing resources of the interposer. Applying an efficient topology and deadlock-free routing algorithm on the CPU layer and interposer layer is essential. In this paper, a new topology and routing algorithm are proposed to use on the CPU layer as well as on the interposer layer for creating a uniform interconnection network to decrease delay and power consumption. This topology is scalable and can be used simply for extensive networks. Most of interposer layer topologies are not scalable and have a lot of crossed links. Moreover, it is required to increase the degree of routers connected to memory segments. The proposed topology uses a few crossed links compared to other proposed interposer layer topologies. There will be some similar small sub-networks that fairly connected together with intermediate routers. Furthermore, this topology can be extended in a hierarchical manner.Trans Emerging Tel Tech. 2019;30:e3747.wileyonlinelibrary.com/journal/ett

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Technology assessment of silicon interposers for manycore SoCs: Active, passive, or optical?

Cited by 10 publications

References 4 publications

Analytical models of AC inductance and quality factor for TSV-based inductor

Analytical models of AC inductance and quality factor for TSV-based inductor

POPSTAR: a Robust Modular Optical NoC Architecture for Chiplet-based 3D Integrated Systems

An expandable topology with low wiring congestion for silicon interposer‐based network‐on‐chip systems

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