POPSTAR: a Robust Modular Optical NoC Architecture for Chiplet-based 3D Integrated Systems

Abstract

Silicon photonics technology is now gaining maturity with increasing levels of design complexity from devices to large photonic integrated circuits. Close integration of control electronics with 3D assembly of photonics and CMOS opens the way to high-performance computing architectures partitioned in chiplets connected by optical NoC on silicon photonic interposers. In this paper, we give an overview of our works on optical links and NoC for manycore systems, from low-level control of photonic devices to high-level system optimization of the optical communications. We detail the POPSTAR optical NoC topology and architecture (Processors On Photonic Silicon interposer Terascale ARchitecture) with electro-optical interface chiplets, the corresponding nested spiral topology for single-writer multiplereader links and the associated control electronics, in charge of high-speed drivers, thermal stabilization and handling of the protocol stack, from data integrity to flow-control, routing and arbitration of the optical communications. The strengths and opportunities for this architecture will be discussed, with a shift in system & implementation constraints with respect to previous optical NoC proposals, and new challenges to be addressed.

Architecting Optically-Controlled Phase Change Memory

“…Moreover, we can multiplex multiple optical signals (up to 32 signals) in a single waveguide, resulting in dense WDM [44]. MicroRing Resonators (MRRs) can modulate these optical signals at data rates up to 12Gbps [5], [67], [86] giving a peak memory throughput of 384Gbps per link. Therefore, it is possible to Fig.…”

“…Silicon-photonic links have enabled high bandwidth-density and low-energy communication between processor and memory [10], [11], [13], [23], [59], [60], [84], [86], [87]. To provide high DRAM internal bandwidth, Beamer et al [13] proposed a joint silicon-photonic link and electro-photonic DRAM design.…”

ReSiPI: A Reconfigurable Silicon-Photonic 2.5D Chiplet Network with PCMs for Energy-Efficient Interposer Communication

“…Although conventional electronic NoCs can efficiently support a small chip with low to medium traffic load, such as at the intra-chiplet level, they impose a high latency when Figure 1: An example of a 2.5D chiplet system with four chiplets connected through an interposer. they are employed on an interposer to handle the global traffic among chiplets [8,16,25]. The high latency of an electronic interposer is due to its long metal interconnects and low inherent bandwidth to support the high volume inter-chiplet traffic.…”

“…Advances in silicon photonics technology [26] have allowed data transmission in PNoCs to benefit from the high throughput, reduced dynamic power, and lower transmission delays of lightspeed communication [18]. The inherent high bandwidth and low latency of PNoCs also makes them a promising solution for interchiplet communication in 2.5D platforms [16,25]. Accordingly, 2.5D chiplet systems with photonic interposer networks have recently received some attention [8,16,25,31].…”

“…The inherent high bandwidth and low latency of PNoCs also makes them a promising solution for interchiplet communication in 2.5D platforms [16,25]. Accordingly, 2.5D chiplet systems with photonic interposer networks have recently received some attention [8,16,25,31]. Such photonic interposer networks can employ wavelength-division multiplexing (WDM) to simultaneously support multiple data streams, each modulated on a different optical wavelength traversing a waveguide, to boost communication bandwidth.…”