Technologies Toward Three-Dimensional Brain-Mimicking IC Architecture

Chin, Albert; Chen, You-Da

doi:10.1109/edtm.2019.8731323

Cited by 8 publications

(9 citation statements)

References 9 publications

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“…Another even more crucial application for CTFTs is used for ultra-low-power and super-fast three-dimensional (3D) brain-mimicking IC [2][3][4] . Although the packaged threedimensional (3D) IC has been applied to Apple's processor, the dynamic switching power (P DS ) and circuit operation speed (f ckt ) has little improvement due to the very low interconnect via density.…”

Section: Challenges and Opportunitiesmentioning

confidence: 99%

“…Such limited f ckt improvement is due to the huge parasitic resistance and capacitance (RC) delay in IC's backend interconnect rather than the frontend transistors, even though the CMOS will soon reach the quantum-mechanical scaling limit in sub-2 nm regime. To overcome this challenge, we pioneered the 3D IC in 2004 3 and 3D brain-mimicking IC 2,4 . The low-temperature formed high-mobility oxide CTFTs can be made directly on the IC's backend inter metal dielectric (IMD) and form the 3D brainmimicking architecture.…”

Section: Challenges and Opportunitiesmentioning

confidence: 99%

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43.2: Invited Paper: High Mobility Oxide Complementary TFTs for System‐on‐Display and Three‐Dimensional Brain‐Mimicking IC

Chin

Yen

Chen

et al. 2021

Symp Digest of Tech Papers

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One technology bottleneck for system‐on‐panel (SoP) is the lacking of high‐performance p‐type thin‐film transistor (pTFT). Using high dielectric‐constant (high‐κ) gate materials with optimized processes, high hole and electron field‐effect mobility of 7.6 and 345 cm2/Vs were measured in pTFT and nTFT, respectively. These high mobility devices on SiO2 are the enabling technology for SoP and crucial for three‐dimensional brain‐mimicking integrated circuit (IC)‐ the technology trend for IC after reaching the quantum‐mechanical limit soon.

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Section: Challenges and Opportunitiesmentioning

confidence: 99%

Section: Challenges and Opportunitiesmentioning

confidence: 99%

43.2: Invited Paper: High Mobility Oxide Complementary TFTs for System‐on‐Display and Three‐Dimensional Brain‐Mimicking IC

Chin

Yen

Chen

et al. 2021

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“…Thin-film transistors (TFTs) have been investigated intensively in the past few decades [1][2][3] because of their ultra-low-energy-using process, usage of a small amount of material, and light transparency [4][5][6][7]. To realize system-on-panel (SoP) and monolithic three-dimensional (3D) integrated circuits (ICs) [8][9][10][11], high-performance n-type and p-type TFT devices (nTFT and pTFT, respectively) are required to form low-DC-power complementary TFTs (CTFTs) [12][13][14][15]. For oxide nTFTs, excellent device performance with a high field-effect mobility (µ FE ), of ~100 cm 2 /V•s; a sharp turn-on subthreshold swing (SS), of ~100 mV/dec; and a large on-current/off-current (I ON /I OFF ) ratio, of >10 6 , has been achieved using a SnO 2 channel material [16][17][18][19][20].…”

Section: Introductionmentioning

confidence: 99%

Remarkably High-Performance Nanosheet GeSn Thin-Film Transistor

et al. 2022

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High-performance p-type thin-film transistors (pTFTs) are crucial for realizing low-power display-on-panel and monolithic three-dimensional integrated circuits. Unfortunately, it is difficult to achieve a high hole mobility of greater than 10 cm2/V·s, even for SnO TFTs with a unique single-hole band and a small hole effective mass. In this paper, we demonstrate a high-performance GeSn pTFT with a high field-effect hole mobility (μFE), of 41.8 cm2/V·s; a sharp turn-on subthreshold slope (SS), of 311 mV/dec, for low-voltage operation; and a large on-current/off-current (ION/IOFF) value, of 8.9 × 106. This remarkably high ION/IOFF is achieved using an ultra-thin nanosheet GeSn, with a thickness of only 7 nm. Although an even higher hole mobility (103.8 cm2/V·s) was obtained with a thicker GeSn channel, the IOFF increased rapidly and the poor ION/IOFF (75) was unsuitable for transistor applications. The high mobility is due to the small hole effective mass of GeSn, which is supported by first-principles electronic structure calculations.

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“…Metal-oxide Thin film transistors (TFTs) have drawn considerable attention due to their high mobility, low fabrication temperature, and simple fabrication process, making them suitable for advanced display [1][2][3][4][5][6] and monolithic three-dimensional (3D) integrated circuit (IC) [15][16][17][18][19][20][21] on amorphous inter-metal-dielectric (IMD) of a Si chip. To reach low DC power consumption, both high performance n-and p-type TFTs are necessary to form the complementary metal-oxide-semiconductor (CMOS) logic.…”

Section: Introductionmentioning

confidence: 99%

“…Moreover, the weak Sn-O bond enthalpy [38] facilitates Sn diffusion into high-dielectric-constant (high-κ) HfO 2 insulator at elevated temperature, 2 of 11 thus degrading device performance. In this study, the above challenges were successfully overcome, and high-performance top-gate nanosheet SnO p-TFT was achieved with high µ FE of 4.4 cm 2 /Vs, large I ON /I OFF of 1.2 × 10 5 , and sharp SS of 526 mV/decade, indicating a high potential for future monolithic 3D and brain-mimicking IC applications [15,[17][18][19][20][21].…”

Section: Introductionmentioning

confidence: 99%

Exceedingly High Performance Top-Gate P-Type SnO Thin Film Transistor with a Nanometer Scale Channel Layer

2021

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Implementing high-performance n- and p-type thin-film transistors (TFTs) for monolithic three-dimensional (3D) integrated circuit (IC) and low-DC-power display is crucial. To achieve these goals, a top-gate transistor is preferred to a conventional bottom-gate structure. However, achieving high-performance top-gate p-TFT with good hole field-effect mobility (μFE) and large on-current/off-current (ION/IOFF) is challenging. In this report, coplanar top-gate nanosheet SnO p-TFT with high μFE of 4.4 cm2/Vs, large ION/IOFF of 1.2 × 105, and sharp transistor’s turn-on subthreshold slopes (SS) of 526 mV/decade were achieved simultaneously. Secondary ion mass spectrometry analysis revealed that the excellent device integrity was strongly related to process temperature, because the HfO2/SnO interface and related μFE were degraded by Sn and Hf inter-diffusion at an elevated temperature due to weak Sn–O bond enthalpy. Oxygen content during process is also crucial because the hole-conductive p-type SnO channel is oxidized into oxygen-rich n-type SnO2 to demote the device performance. The hole μFE, ION/IOFF, and SS values obtained in this study are the best-reported data to date for top-gate p-TFT device, thus facilitating the development of monolithic 3D ICs on the backend dielectric of IC chips.

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Technologies Toward Three-Dimensional Brain-Mimicking IC Architecture

Cited by 8 publications

References 9 publications

43.2: Invited Paper: High Mobility Oxide Complementary TFTs for System‐on‐Display and Three‐Dimensional Brain‐Mimicking IC

43.2: Invited Paper: High Mobility Oxide Complementary TFTs for System‐on‐Display and Three‐Dimensional Brain‐Mimicking IC

Remarkably High-Performance Nanosheet GeSn Thin-Film Transistor

Exceedingly High Performance Top-Gate P-Type SnO Thin Film Transistor with a Nanometer Scale Channel Layer

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