Nonstoichiometric silicon oxide SiOx is a promising material for developing a new generation of high-speed, reliable flash memory based on the resistive effect. It is necessary to understand the electron transport mechanism of the high-resistive state in SiOx to develop a resistive memory element. At present, it is generally accepted that the charge transport of the high-resistive state in the Resistive Random Access Memory (RRAM) is described by the Frenkel effect. In our work, the charge transport of the high-resistive state in RRAM based on SiOx is analyzed with two contact-limited and five volume-limited charge transport models. It is established that the Schottky effect model, thermally assisted tunneling, the Frenkel model of Coulomb trap ionization, the Makram-Ebeid and Lannoo model of multiphonon isolated trap ionization, and the Nasyrov-Gritsenko model of phonon-assisted tunneling between traps, quantitatively, do not describe the charge transport of the high-resistive state in the RRAM based on SiOx. The Shklovskii-Efros percolation model gives a consistent explanation for the charge transport of the high-resistive state in the RRAM based on SiOx at temperatures above room temperature.

All-nonmetal resistive random access memory (RRAM) with a n + -Si/Sin x /p + -Si structure was investigated in this study. the device performance of Sin x developed using physical vapor deposition (PVD) was significantly better than that of a device fabricated using plasma-enhanced chemical vapor deposition (pecVD). the Sin x RRAM device developed using pVD has a large resistance window that is larger than 10 4 and exhibits good endurance to 10 5 cycles under switching pulses of 1 μs and a retention time of 10 4 s at 85 °C. Moreover, the SiN x RRAM device developed using pVD had tighter device-todevice distribution of set and reset voltages than those developed using pecVD. Such tight distribution is crucial to realise a large-size cross-point array and integrate with complementary metal-oxidesemiconductor technology to realise electronic neurons. the high performance of the Sin x RRAM device developed using pVD is attributed to the abundant defects in the pVD dielectric that was supported by the analysed conduction mechanisms obtained from the measured current-voltage characteristics.Resistive random access memory (RRAM) 1-26 has attracted considerable attention over the past two decades due to its simple structure, nonvolatility, high scalability, rapid switching speed, and relatively low operating power. These advantages make RRAM devices suitable for use in future artificial intelligence and neuromorphic computing applications 1-4 . A variety of binary composite materials, such as HfO x , TaO x , TiO x , SiO x , and GeO x , that exhibit different device properties have been used as the switching layer. Although various conduction mechanisms for RRAMs have been proposed, the carrier transport behaviour of RRAMs still has not been completely confirmed. To prevent the metal ions from contributing to transport behaviour, we pioneered nonmetal GeO x dielectric RRAM devices 6-10 and all-nonmetal N + -Si/SiO x /P + -Si RRAM devices 11 . In this study, we investigated the all-nonmetal SiN x RRAM devices in which the bond enthalpy of SiN is lower than that of SiO 27 . The SiN x material has been widely used in the semiconductor industry for various applications, such as the passivation layer of an integrated circuit and the charge-trapping layer of a flash memory. This material can be easily integrated into complementary metal-oxide-semiconductor (CMOS) technology. Moreover, the RRAM device performance strongly depends on the SiN x formation process. A high-performance RRAM device with a large memory window, good endurance, long retention time, and tight device-to-device distribution of the set-reset voltages V set -V reset is only achievable when the SiN x layers are formed using low-temperature physical vapor deposition (PVD) rather than the standard plasma-enhanced chemical vapor deposition (PECVD). The high-performance SiN x RRAM device developed using PVD (PVD-SiN x RRAM device) is linked to the high number of defects and high amount of defect-related current conduction in the SiN x dielectric.

Amorphous silicon nitride is a key dielectric in silicon devices. The advantage of SiNx and Si3N4 over other dielectrics is that silicon nitride is compatible with silicon technology and is widely used in it. It is necessary to understand, experimentally and theoretically, the mechanism of charge transport in a memristor based on silicon nitride in the initial, high-resistance, and low-resistance states to develop a resistive memory element. At present, there is currently no single universal model of charge transport in a memristor based on silicon nitride. In our work, the charge transport of the initial, high, and low resistive states in an SiNx-based memristor is analyzed with four bulk-limited charge transport models. It is established that the Frenkel model of Coulomb traps ionization, Hill-Adachi model of overlapping Coulomb traps, and Makram-Ebeid and Lannoo model of multiphonon isolated traps ionization, quantitatively, do not describe the charge transport of the SiNx-based memristor in any state. The Nasyrov-Gritsenko model of phonon-assisted tunneling between traps gives a consistent explanation of the charge transport of the SiNx-based memristor in all states at temperatures above room temperature.

Metal-oxide thin-film transistors (TFTs) have been implanted for a display panel, but further mobility improvement is required for future applications. In this study, excellent performance was observed for top-gate coplanar binary SnO2 TFTs, with a high field-effect mobility (μFE) of 136 cm2/Vs, a large on-current/off-current (ION/IOFF) of 1.5 × 108, and steep subthreshold slopes of 108 mV/dec. Here, μFE represents the maximum among the top-gate TFTs made on an amorphous SiO2 substrate, with a maximum process temperature of ≤ 400 °C. In contrast to a bottom-gate device, a top-gate device is the standard structure for monolithic integrated circuits (ICs). Such a superb device integrity was achieved by using an ultra-thin SnO2 channel layer of 4.5 nm and an HfO2 gate dielectric with a 3 nm SiO2 interfacial layer between the SnO2 and HfO2. The inserted SiO2 layer is crucial for decreasing the charged defect scattering in the HfO2 and HfO2/SnO2 interfaces to increase the mobility. Such high μFE, large ION, and low IOFF top-gate SnO2 devices with a coplanar structure are important for display, dynamic random-access memory, and monolithic three-dimensional ICs.

Traditional Resistive Random Access Memory (RRAM) is a metal-insulator-metal (MIM) structure, in which metal oxide is usually used as an insulator. The charge transport mechanism of traditional RRAM is attributed to a metallic filament inside the RRAM. In this paper, we demonstrated a novel RRAM device with no metal inside. The N + -Si/SiO x /P + -Si combination forms a N + IP + diode structure that is different from traditional MIM RRAM. A large high-resistance/low-resistance window of 1.9 × 10 4 was measured at room temperature. A favorable retention memory window of 1.2 × 10 3 was attained for 10 4 s at 85 °C. The charge transport mechanism of virgin, high- and low-resistance states can be well modeled by the single Shklovskii-Efros percolation mechanism rather than the charge transport in metallic filament. X-ray photoelectron spectroscopy demonstrated that the value of x in SiO x was 0.62, which provided sufficient oxygen vacancies for set/reset RRAM functions.

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Large device variation is a fundamental challenge for resistive random access memory (RRAM) array circuit. Improved device-to-device distributions of set and reset voltages in a SiNx RRAM device is realized via arsenic ion (As+) implantation. Besides, the As+-implanted SiNx RRAM device exhibits much tighter cycle-to-cycle distribution than the nonimplanted device. The As+-implanted SiNx device further exhibits excellent performance, which shows high stability and a large 1.73 × 103 resistance window at 85 °C retention for 104 s, and a large 103 resistance window after 105 cycles of the pulsed endurance test. The current–voltage characteristics of high- and low-resistance states were both analyzed as space-charge-limited conduction mechanism. From the simulated defect distribution in the SiNx layer, a microscopic model was established, and the formation and rupture of defect-conductive paths were proposed for the resistance switching behavior. Therefore, the reason for such high device performance can be attributed to the sufficient defects created by As+ implantation that leads to low forming and operation power.

One technology bottleneck for system‐on‐panel (SoP) is the lacking of high‐performance p‐type thin‐film transistor (pTFT). Using high dielectric‐constant (high‐κ) gate materials with optimized processes, high hole and electron field‐effect mobility of 7.6 and 345 cm2/Vs were measured in pTFT and nTFT, respectively. These high mobility devices on SiO2 are the enabling technology for SoP and crucial for three‐dimensional brain‐mimicking integrated circuit (IC)‐ the technology trend for IC after reaching the quantum‐mechanical limit soon.