2013
DOI: 10.1145/2555289.2555299
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Techniques to improve performance in requester-wins hardware transactional memory

Abstract: The simplicity of requester-wins Hardware Transactional Memory (HTM) makes it easy to incorporate in existing chip multiprocessors. Hence, such systems are expected to be widely available in the near future. Unfortunately, these implementations are prone to suffer severe performance degradation due to transient and persistent livelock conditions. This article shows that existing techniques are unable to mitigate this degradation effectively. It then proposes and evaluates four novel techniques-two software-bas… Show more

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Cited by 1 publication
(1 citation statement)
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“…Several applied papers, e.g. [16,9,23,11] discuss the trade-offs involved in implementing transactional protocols in hardware, and the performance pathologies of such systems. Reference [23] explicitly discusses the possibility of adding delays to hardware transactions, and implements and compares heuristics for tuning these delays.…”
Section: Related Workmentioning
confidence: 99%
“…Several applied papers, e.g. [16,9,23,11] discuss the trade-offs involved in implementing transactional protocols in hardware, and the performance pathologies of such systems. Reference [23] explicitly discusses the possibility of adding delays to hardware transactions, and implements and compares heuristics for tuning these delays.…”
Section: Related Workmentioning
confidence: 99%