Techniques to Enable FPGA Based Reconfigurable Fault Tolerant Space Computing

Smith, Gerald L.; Torre, Luís de la

doi:10.1109/aero.2006.1655958

Cited by 20 publications

(9 citation statements)

References 5 publications

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“…Finally, the speed of the system decreases due to the addition of a new stage. Some representative applications can be found at the literature [54]- [56].…”

Section: ) Triple Modular Redundancymentioning

confidence: 99%

Single Event Effects on Digital Integrated Circuits: Origins and Mitigation Techniques

Velazco

Franco

2007

2007 IEEE International Symposium on Industrial Electronics

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Abstract-New generation electronic devices have become more and more sensitive to the effects of the natural radiation coming from the surrounding environment. These radiation sources are cosmic rays and radioactive impurities, able to corrupt the content of memory cells or to induce transient pulses in combinational logic. The growing sensitivity seems to be related to two main factors: the lower and lower charge needed to define the logic levels in advanced devices and the increasing number of basic components inside the modern integrated circuits. In this paper, are described state-of-art techniques to mitigate these effects as well as typical tests to verify the radiation-tolerance of the devices and/or systems.

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“…Finally, the speed of the system decreases due to the addition of a new stage. Some representative applications can be found at the literature [54]- [56].…”

Section: ) Triple Modular Redundancymentioning

confidence: 99%

Single Event Effects on Digital Integrated Circuits: Origins and Mitigation Techniques

Velazco

Franco

2007

2007 IEEE International Symposium on Industrial Electronics

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“…In literature, when considering multi-FPGA platforms, the available devices are usually exploited to host replicas of the main system as in Smith and de la Torre [2006], where three FPGAs are used to apply the classical Triple Modular Redundancy (TMR) technique on the whole circuit. Each FPGA hosts the same configuration and an external radiation-hardened ASIC implements a controller that acts as a TMR voter.…”

Section: Related Workmentioning

confidence: 99%

Design of Hardened Embedded Systems on Multi-FPGA Platforms

Bolchini

Sandionigi

2014

ACM Trans. Des. Autom. Electron. Syst.

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The aim of this article is the definition of a reliability-aware methodology for the design of embedded systems on multi-FPGA platforms. The designed system must be able to detect the occurrence of faults globally and autonomously, in order to recover or to mitigate their effects. Two categories of faults are identified, based on their impact on the device elements; (i) recoverable faults, transient problems that can be fixed without causing a lasting effect namely and (ii) nonrecoverable faults, those that cause a permanent problem, making the portion of the fabric unusable. While some aspects can be taken from previous solutions available in literature, several open issues exist. In fact, no complete design methodology handling all the peculiar issues of the considered scenario has been proposed yet, a gap we aim at filling with our work. The final system exposes reliability properties and increases its overall lifetime and availability

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“…The other designs exclude certain components, and these are compared with design 1 so percentage hardware overhead can be calculated. To put these figures in context, triple modular redundancy (TMR, the most prevalent testing method currently used, where each system is triplicated and the results combined using majority voting hardware [22]) requires 200% overhead plus a non-trivial amount of extra for the voting circuitry; if voting is done at a functional (as opposed to system) level, overheads as high as 700% are reported [25]. Further, in Unitronics, only one external controller (UXC) is needed for several arrays of cells, so its overhead of 28.9% (found by comparing design 3 and 4) relative to one cell can be considered negligible when compared to several arrays of several hundred cells each.…”

Section: Hardware Overhead Of Test and Repair Mechanismsmentioning

confidence: 99%

SABRE: a bio-inspired fault-tolerant electronic architecture

Bremner¹,

Liu²,

Samie³

et al. 2013

Bioinspir. Biomim.

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As electronic devices become increasingly complex, ensuring their reliable, fault-free operation is becoming correspondingly more challenging. It can be observed that, in spite of their complexity, biological systems are highly reliable and fault tolerant. Hence, we are motivated to take inspiration for biological systems in the design of electronic ones. In SABRE (self-healing cellular architectures for biologically inspired highly reliable electronic systems), we have designed a bio-inspired fault-tolerant hierarchical architecture for this purpose. As in biology, the foundation for the whole system is cellular in nature, with each cell able to detect faults in its operation and trigger intra-cellular or extra-cellular repair as required. At the next level in the hierarchy, arrays of cells are configured and controlled as function units in a transport triggered architecture (TTA), which is able to perform partial-dynamic reconfiguration to rectify problems that cannot be solved at the cellular level. Each TTA is, in turn, part of a larger multi-processor system which employs coarser grain reconfiguration to tolerate faults that cause a processor to fail. In this paper, we describe the details of operation of each layer of the SABRE hierarchy, and how these layers interact to provide a high systemic level of fault tolerance.

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Techniques to Enable FPGA Based Reconfigurable Fault Tolerant Space Computing

Cited by 20 publications

References 5 publications

Single Event Effects on Digital Integrated Circuits: Origins and Mitigation Techniques

Single Event Effects on Digital Integrated Circuits: Origins and Mitigation Techniques

Design of Hardened Embedded Systems on Multi-FPGA Platforms

SABRE: a bio-inspired fault-tolerant electronic architecture

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