Techniques for SAT-based constrained test pattern generation

Abstract

Abstract-Testing of digital circuits seems to be a completely mastered part of the design flow, but constrained test patterns generation is still a highly evolving branch of digital circuit testing. Our previous research on constrained test pattern generation proved that we can benefit from an implicit representation of test patterns set in CNF (Conjunctive Normal Form). Some techniques of speeding up the constrained SATbased test patterns generation are described and closely analyzed in this paper. These techniques are experimentally evaluated on a real SAT-based algorithm performing a constrained test patterns compression based on overlapping of test patterns. Experiments are performed on a subset of ISCAS'85 and '89 benchmark circuits. Results of the experiments are discussed and recommendations for a further development of similar SAT-based tools for constrained test patterns generation are given.

PBO-Based Test Compression

“…All test vectors for a given fault are represented as solutions of a Boolean satisfiability problem (SAT) instance. This is also the case of SAT-Compress algorithm [8] referenced in this paper. Using implicit test representations, we do not lose any information, when the test is generated and passed to the compression process.…”

“…The principles of the PBO-Compress algorithm are the same as those of SAT-Compress [8], except of the test patterns generation, where instead of generating and solving SAT for each fault, a PBO instance is generated and solved. For the complete algorithm see [8] and [20].…”

“…The compression is based on overlapping of shifted test vectors [8], [9]. In an optimal case, values of two subsequent test vectors are displaced by one bit, with one bit added.…”

Artificial Bee Colony and Neural Networks Optimization Test Generation Algorithm for Multiple Faults of Digital Circuits

“…The states are called consistent states when the states satisfy the circuit's function; other states are called inconsistent states when they can't satisfy the circuit's function [11] . The energy function's value is zero if the neuron states are consistent with the function of the circuit and energy function's value is greater than zero for all inconsistent states.…”

Improved SAT-based ATPG: More constraints, better compaction

“…The application of SAT for test compression schemes is treated in [24]. The concept of dynamic compaction was transferred to the SAT-based ATPG domain in [25].…”