Techniques for reducing the reverse short channel effect in sub-0.5 μm CMOS

Lutze, J.; Venkatesan, S.

doi:10.1109/55.406792

Cited by 19 publications

(6 citation statements)

References 8 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Properly predicting its evolution and magnitude is of key importance in designing submicron devices. [1][2][3] The evaporation of ͕311͖ silicon self-interstitial clusters has recently been linked to the phenomenon of TED. 4 The time for cluster evaporation was found to be similar to the duration of transient diffusion over the temperature range 670-815°C, and the measured dose of interstitials in the clusters was consistent with the doses required to match simulations of TED with data.…”

mentioning

confidence: 99%

Simulation of cluster evaporation and transient enhanced diffusion in silicon

Rafferty

Gilmer

Jaraı́z

et al. 1996

Applied Physics Letters

150

View full text Add to dashboard Cite

The evaporation of {311} self-interstitial clusters has recently been linked to the phenomenon of transient enhanced diffusion in silicon. A theory of cluster evaporation is described, based on first-order kinetic equations. It is shown to give a good account of the data over a range of temperatures. The theory simultaneously explains several of the unexpected features of transient enhanced diffusion, including the apparently steady level of the enhancement during its duration, and the dependence of the duration on implant energy and dose. The binding energy used to match the theory to data is in good agreement with molecular dynamics calculations of cluster stability in silicon.

show abstract

mentioning

confidence: 99%

Simulation of cluster evaporation and transient enhanced diffusion in silicon

Rafferty

Gilmer

Jaraı́z

et al. 1996

Applied Physics Letters

150

View full text Add to dashboard Cite

show abstract

“…A scaling-down of gate length has a significant effect on the device characteristics. As in the case of conventional MOSFETs, gate length (L G ) scaling-down causes the short channel effect (SCE), 27,28) increase in the slope of the diffusion-current. Also, in this hybrid MOSFET, L G scaling-down is simultaneously accompanied by L 1 =L 2 scaling-down.…”

Section: Gate Lengthmentioning

confidence: 99%

Proposal of tunneling- and diffusion-current hybrid MOSFET: A device simulation study

Furukawa

Teramoto

Kuroda

et al. 2016

Jpn. J. Appl. Phys.

View full text Add to dashboard Cite

Transistors with low-power operation and sufficient signal processing speed have been widely required especially for mobile applications. To meet these requirements, we propose a novel tunneling- and diffusion-current hybrid MOSFETs which utilize both a small S-factor of tunneling-current and a high current drivability of diffusion-current. On the basis of the device concept and the working principle that we propose, device structures and parameters of the hybrid MOSFET were examined in detail with device simulation. We investigated the optimum structure of the tunneling and diffusion parts, and the effects of various structural parameters. In particular, we found that the threshold voltage adjustment of each current and the suppression of leakage current were the most important to maximize the characteristics of the hybrid MOSFET. From the result of structural parameter optimization, a minimum S-factor of 20 mV/decade and a high current drivability of 500 µA/µm were obtained simultaneously. In addition, a process flow idea to fabricate three-dimensional structure hybrid MOSFETs with tunneling-current side channels and diffusion-current top channel is presented.

show abstract

“…The evolution of the semiconductor industry, as predicted by the international technology roadmap for semiconductors (ITRS) [1], shall lead to the minimum size of transistors decreases in future years. As the MOSFET gate length enters nanometers scale, short channel effect such as threshold voltage roll-off and drain-induced-barrierlowering effect become increasingly significant, which limits the scaling capability of MOSFET [2,3]. Because of these effects some equations are added such as quantum mechanical equations [4,5].…”

Section: Introductionmentioning

confidence: 99%

Modeling double gate FinFETs by using artificial neural network

Abtin

Keshavarzi

Jaferzadeh

et al. 2010

2010 IEEE International Conference on Semiconductor Electronics (ICSE2010)

View full text Add to dashboard Cite

The minimum feature size of the transistors will be decreases in the future years as predicted by the international technology roadmap for semiconductors. Multi-gate FETs such as FinFETs have emerged as the most promising candidates to extend the CMOS scaling into the sub-25nm regime when considering the low scale effects is important for decreasing the scale. Solving and simulating the equations of these devices are so complicated and time consuming. In this paper we use RBF network for simulating the I-V characteristics of common symmetric multi gate FinFETs by using some BSIM-CMG data as a database for training. The results show a good agreement between RBF network and BSIM-CMG. The maximum error between BSIM-CMG and RBF is only 1%. The RBF is used for simulating or predicting I-V curve for different inputs without solving the complicated equations.

show abstract

Techniques for reducing the reverse short channel effect in sub-0.5 μm CMOS

Cited by 19 publications

References 8 publications

Simulation of cluster evaporation and transient enhanced diffusion in silicon

Simulation of cluster evaporation and transient enhanced diffusion in silicon

Proposal of tunneling- and diffusion-current hybrid MOSFET: A device simulation study

Modeling double gate FinFETs by using artificial neural network

Contact Info

Product

Resources

About