TDO-CIM: Transparent Detection and Offloading for Computation In-memory

Vadivel, Kanishkan; Chelini, Lorenzo; BanaGozar, Ali; Singh, Gagandeep; Corda, Stefano; Jordans, Roel; Corporaal, Henk

doi:10.23919/date48585.2020.9116464

Cited by 9 publications

(4 citation statements)

References 26 publications

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“…Unfortunately, previous CIM-oriented compilation frameworks overlook the aforementioned deployment issues. For example, frameworks like TC-CIM [28], TDO-CIM [29], and OCC [30] regard the CIM macro as an abstract model similar to the tensor core, which is a type of processing element of graphic processing units (GPUs) [31]. However, operator incompatibility and macro utilization are not evaluated and discussed in these works.…”

Section: (C) Most Previous Work Evaluate Cnns On Lightweightmentioning

confidence: 99%

“…In this section, the deployment results of convolution-based algorithms are analyzed. The evaluation is conducted based on a cost model of an SRAM-CIM system [28][29][30]. First, the proposed weight mapping strategies are evaluated across different convolution layers.…”

Section: Experimental Evaluationmentioning

confidence: 99%

“…Table III provides a comparison between the proposed framework and previous CIM-oriented compilation frameworks [28][29][30]. It is important to note that the previous frameworks, such as TC-CIM, TDO-CIM, and OCC, were developed for PCM-CIM systems [28][29][30] which have a different computational model compared to SRAM-CIM systems. This paper introduces a dedicated framework specifically designed for SRAM-CIM systems, supporting both bit-flexible quantization and error correction schemes.…”

Section: E Comparison With Previous Workmentioning

confidence: 99%

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A Compilation Framework for SRAM Computing-in-Memory Systems with Optimized Weight Mapping and Error Correction

Bai,

Li,

Zhang

et al. 2024

Preprint

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Deploying convolution-based algorithms into SRAM computing-in-memory (CIM) systems faces various challenges, such as operator incompatibility and intrinsic non-ideal error. This paper proposes a compilation framework to address this issue. Efficient weight mapping strategies are introduced to improve the utilization of SRAM-CIM macro. The intrinsic non-ideal errors of SRAM-CIM macro are also taken into consideration, and two efficient error correction schemes are proposed, which include calibration of computation voltage linear error (CCVLE) and the mitigation of analog-to-digital quantization error (MAQE). In addition, bit-width flexibility and signed-unsigned reconfigurability are also supported to facilitate the deployment of various convolution-based algorithms. ResNet18, finite impulse response (FIR) filtering, and Gaussian image filtering are deployed into a multi-macro SRAM-CIM system. These algorithms serve as deployment representatives of convolutional neural network (CNN), digital signal processing (DSP), and digital image processing (DIP), respectively. The results show that the introduced weight mapping strategies improve the macro utilization by 63.29% and 21.10% for two types of frequently used convolution layers compared to the traditional strategy. Moreover, the proposed error correction schemes achieve similar algorithm accuracy to the floating-point results, and the deployment result of ResNet18 achieves 66.3%~70.1% top-1 classification accuracy evaluated on the ImageNet dataset with different throughput tradeoffs.

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Section: (C) Most Previous Work Evaluate Cnns On Lightweightmentioning

confidence: 99%

Section: Experimental Evaluationmentioning

confidence: 99%

Section: E Comparison With Previous Workmentioning

confidence: 99%

See 1 more Smart Citation

A Compilation Framework for SRAM Computing-in-Memory Systems with Optimized Weight Mapping and Error Correction

Bai,

Li,

Zhang

et al. 2024

Preprint

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“…There have been attempts at making everything transparent to the programmer by reworking existing parallel computing frameworks such as Apache Spark, MapReduce, [51][52][53] and MPI [10]. Alternately, compilers automatically identify and transform these regions appropriately to a form suitable for the targeted PIM architecture [28,31,64]. Our work falls into the last camp.…”

Section: Programming Models For Pimmentioning

confidence: 99%

To PIM or not for emerging general purpose processing in DDR memory systems

Devic

Balakrishna

Sivasubramaniam

et al. 2022

Proceedings of the 49th Annual International Symposium on Computer Architecture

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As Processing-In-Memory (PIM) hardware matures and starts making its way into normal compute platforms, software has an important role to play in determining what to perform where, and when, on such heterogeneous systems. Taking an emerging class of PIM hardware which provisions a general purpose (RISC-V) processor at each memory bank, this paper takes on this challenging problem by developing a software compilation framework. This framework analyzes several application characteristics -parallelizability, vectorizability, data set sizes, and offload costs -to determine what, whether, when and how to offload computations to the PIM engines. In the process, it also proposes a vector engine extension to the bank-level RISC-V cores. Using several off-the-shelf C/C++ applications, we demonstrate that PIM is not always a panacea, and a framework such as ours is essential in carefully selecting what needs to be performed where, when and how. The choice of hardware platforms -number of memory banks, relative speeds and capabilities of host CPU and PIM cores, can further impact the "to PIM or not" question. CCS CONCEPTS• Computer systems organization → Heterogeneous (hybrid) systems; • Hardware → Emerging architectures; Emerging languages and compilers.

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