TCAD structure synthesis and capacitance extraction of a voltage-controlled oscillator using automated layout-to-device synthesis methodology

Abstract

With continued scaling of bulk CMOS devices in the nanometer regime, technology computer-aided design (TCAD) assisted extraction of parasitic capacitances has gained importance for predicting the transient behavior of VLSI circuits. In this paper, we present a TCAD structure synthesis and capacitance extraction methodology in a 22nm CMOS process and report parasitic capacitances that affect the oscillation frequency of a 10 GHz voltage-controlled oscillator (VCO). We observe that front-end capacitances are becoming overwhelmingly dominant at nanometer nodes. We quantify the capacitive interactions between the front-end and back-end features using a layer-bylayer capacitance analysis. The estimated frequency tuning range is in agreement with the tuning range of a 22nm VCO hardware.