TCAD predictions of hot-electron injection in p-type LDMOS transistors

Giuliano, Federico; Depetro, Riccardo; Croce, Giuseppe; Tallarico, Andrea Natale; Reggiani, Susanna; Gnudi, Antonio; Sangiorgi, E.; Fiegna, Claudio; Rossetti, M.; Molfese, A.; Manzini, Stefano

doi:10.1109/essderc.2019.8901703

Cited by 5 publications

(4 citation statements)

References 12 publications

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“…Unlike the n-channel counterpart, in which the II is purely dominated by the majority carriers, in p-channel devices minority ones play a fundamental role as well. To separate the two effects, the II coefficients for electrons (EII) and holes (HII) of the UniBo2 TCAD model [9] have been calibrated on n-channel LDMOS transistors [10] and ad-hoc p-channel 5V-MOSFETs [11], respectively. As shown in Fig.…”

Section: Resultsmentioning

confidence: 99%

Full Understanding of Hot Electrons and Hot/Cold Holes in the Degradation of p-channel Power LDMOS Transistors

Tallarico

Reggiani

Depetro

et al. 2020

2020 IEEE International Reliability Physics Symposium (IRPS)

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Section: Resultsmentioning

confidence: 99%

Full Understanding of Hot Electrons and Hot/Cold Holes in the Degradation of p-channel Power LDMOS Transistors

Tallarico

Reggiani

Depetro

et al. 2020

2020 IEEE International Reliability Physics Symposium (IRPS)

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“…A. Simulation model TCAD (Technology computer-aided design) simulation has already played an increasingly significant role in the LDMOS device structure designs [27] [28]. For a CFP device, modulation factor is strongly related to the device's physical dimension, including field plate length L, effective field plate thickness H, and slot field plate contact width W.…”

Section: Field Plate L/w/h Effects and Discussionmentioning

confidence: 99%

Design and Simulation Optimization of an Ultra-Low Specific On-Resistance LDMOS Device

Yu,

Shao,

Chen

et al. 2024

IEEE J. Electron Devices Soc.

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The design of LDMOS (Lateral double diffused metal oxide semiconductor) devices with CFP (Contact field plate) has been of great significance in recent years, according to its advantages of low resistance and high switch efficiency. In this paper, this ultra-low , (Specific on-resistance) LDMOS device is simulated, designed, and fabricated. The effects on FOM (Figures-of-merits) characters from physical dimensions, including field plate length L, field plate thickness H, and slot contact width W, have been analyzed and discussed. The best device structure is proposed through simulation, and a related fabrication process is introduced correspondingly. Finally, the electrical measurement results show that , can achieve as low as 6.9m•mm 2 when the source-drain (Breakdown voltage) arrives at 34.1V, which is improved by 47.1% compared with conventional devices. Furthermore, the TLP (Transmission line pulse) test results indicate that the device owns an ideal SOA (Safe operation area) from both typical devices (W=10 m) and very large devices (W= 2mm). Index Terms-Contact field plate (CFP), Figures of merits (FOM), Lateral double diffusion metal oxide semiconductor (LDMOS), Specific on-resistance ( , )

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“…For further study on the effects of "abrupt" field plate bottom profile on device performance, TCAD simulation [11,15] is carried out with the 2-D models of Sivaco software.…”

Section: Technology Computer-aided Design (Tcad) Simulationmentioning

confidence: 99%

A Process Optimization Method of the Mini-LOCOS Field Plate Profile for Improving Electrical Characteristics of LDMOS Device

Yu,

Shao,

Gao

et al. 2023

IET Circuits, Devices & Systems

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In this work, the effects of the mini-local oxidation of silicon (LOCOS) field plate’s bottom physical profile on the devices’ breakdown performance are analyzed through technology computer-aided design simulations. It is indicated that the “abrupt” bottom profile could certainly do with an optimization. This paper introduces an effective process improvement method by etching bias power adjustment and time reduction. The upgradation of the field plate physical profile has been proved by transmission electron microscope cross-section analysis. The angle for the bottom surface of mini-LOCOS field plate θ2 is improved from 11.9° to 12.6°, and the thickness ratio of Hup/Hbottom (field plate oxide thickness for the upper and bottom, respectively) is increased from 71.8% to 76.6%. Finally, the optimized laterally diffused metal oxide semiconductor devices have been fabricated, and both figure of merit curves and safe operation area curves are measured. The specific on-resistance Ron,sp could achieve as low as 11.3 mΩ mm2, while breakdown voltage BVds,max arrives at 37.4 V, which is nearly 19.3% improved.

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TCAD predictions of hot-electron injection in p-type LDMOS transistors

Cited by 5 publications

References 12 publications

Full Understanding of Hot Electrons and Hot/Cold Holes in the Degradation of p-channel Power LDMOS Transistors

Full Understanding of Hot Electrons and Hot/Cold Holes in the Degradation of p-channel Power LDMOS Transistors

Design and Simulation Optimization of an Ultra-Low Specific On-Resistance LDMOS Device

A Process Optimization Method of the Mini-LOCOS Field Plate Profile for Improving Electrical Characteristics of LDMOS Device

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