TCAD for reliability

Pfäffli, Paul; Tikhomirov, P. V.; Xu, Xiaopeng; Avci, I.; Oh, Yong‐Seog; Balasingam, Pratheep; Krishnamoorthy, S.; Ma, Tingting

doi:10.1016/j.microrel.2012.06.025

Cited by 8 publications

(3 citation statements)

References 15 publications

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“…In this study, V T extraction was followed the constant current methodology. To accelerate the process and circuit development in yield and reliability analysis in the nano-node era, the technology computer-aided design simulator is an appropriate choice as an assistant [23][24][25].…”

Section: Purpose Stress Methods Specificationsmentioning

confidence: 99%

Hot Carrier Stress Sensing Bulk Current for 28 nm Stacked High-k nMOSFETs

et al. 2020

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This work primarily focuses on the degradation degree of bulk current (IB) for 28 nm stacked high-k (HK) n-channel metal–oxide–semiconductor field-effect transistors (MOSFETs), sensed and stressed with the channel-hot-carrier test and the drain-avalanche-hot-carrier test, and uses a lifetime model to extract the lifetime of the tested devices. The results show that when IB reaches its maximum, the ratio of VGS/VDS values at this point, in the meanwhile, gradually increases in the tested devices from the long-channel to the short ones, not just located at one-third to one half. The possible ratiocination is due to the ON-current (IDS), in which the short-channel devices provide larger IDS impacting the drain junction and generating more hole carriers at the surface channel near the drain site. In addition, the decrease in IB after hot-carrier stress is not only the increment in threshold voltage VT inducing the decrease in IDS, but also the increment in the recombination rate due to the mechanism of diffusion current. Ultimately, the device lifetime uses Berkley’s model to extract the slope parameter m of the lifetime model. Previous studies have reported m-values ranging from 2.9 to 3.3, but in this case, approximately 1.1. This possibly means that the critical energy of the generated interface state becomes smaller, as is the barrier height of the HK dielectric to the conventional silicon dioxide as the gate oxide.

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Section: Purpose Stress Methods Specificationsmentioning

confidence: 99%

Hot Carrier Stress Sensing Bulk Current for 28 nm Stacked High-k nMOSFETs

et al. 2020

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“…In this paper we have used Technology Computer Aided Design (TCAD) to simulate 1T-NOR Flash Programming window closure after 1 million cycles. TCAD is a physics-based numerical modelling approach for accurately simulating both fabrication process and electrical characteristics of microelectronics devices, a tool that has been successfully used for device performance optimization and reliability improvement [5,6,7]. Similar to [8] Flash endurance was modelled through defects; however, in this paper we have adopted an inhomogeneous defects distribution both at Si/SiO2 interface and in SiO2 bulk oxide, as well as different types of defects.…”

Section: Introductionmentioning

confidence: 99%

1T-NOR Flash memory after endurance degradation: An advanced TCAD simulation

Matteo

Simola

Postel-Pellerin

et al. 2022

Microelectronics Reliability

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“…These very low levels cannot be detected with conventional surface analysis techniques such as Auger electron spectroscopy, X-ray photoelectron spectroscopy, and ultraviolet photoelectron spectroscopy, and are also too low to be detected with usual bulk analysis tools such as secondary ion mass spectrometry, complicating device failure analyses. It is thus necessary to identify contaminant possible effects on fabrication processes, and to be able to simulate contamination redistribution at levels lower than detection limits during device fabrication, in order to potentially identify their influence on device electrical properties [1][2][3].…”

Section: Introductionmentioning

confidence: 99%

Redistribution of Metallic Impurities in Si during Annealing and Oxidation: W and Fe

Portavoce

Luca

Burle

et al. 2018

DDF

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Atomic redistribution of W and Fe in Si were studied using secondary ion mass spectrometry and transmission electron microscopy. W diffusion experiments performed during isothermal annealing and during Si oxidation show that W atoms should use at least two different diffusion mechanisms. Experimental diffusion profiles can be well simulated by considering the simultaneous use of three different W diffusion mechanisms: the dissociative and the kick-out mechanisms, as well as an original mechanism based on the formation of a W-Si self-interstitial pair located on the interstitial Si sub-lattice. Fe redistribution was studied during the oxidation of a Fe-contaminated Si wafer. Fe is shown to be first pushed-out in Si by the mobile SiO2/Si interface, and thus to form Fe silicides precipitates at this interface. The silicide precipitates, which can exhibit a core-shell structure, appear to move with the SiO2/Si interface thanks to an oxidation/dissolution mechanism in the SiO2 and a nucleation/growth mechanism in the Si matrix. Furthermore, the rate difference between Si and Fe silicide precipitate oxidation leads to the formation of Si pyramidal defects at the SiO2/Si interface.

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TCAD for reliability

Cited by 8 publications

References 15 publications

Hot Carrier Stress Sensing Bulk Current for 28 nm Stacked High-k nMOSFETs

Hot Carrier Stress Sensing Bulk Current for 28 nm Stacked High-k nMOSFETs

1T-NOR Flash memory after endurance degradation: An advanced TCAD simulation

Redistribution of Metallic Impurities in Si during Annealing and Oxidation: W and Fe

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