2018 31st IEEE International System-on-Chip Conference (SOCC) 2018
DOI: 10.1109/socc.2018.8618501
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Taxonomy of Spatial Parallelism on FPGAs for Massively Parallel Applications

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Cited by 5 publications
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“…This growth requires an exploitation of modern technologies to enhance and increase this processing in a parallelism manner to achieve high throughput. Various algorithms and devices introduced by researchers to achieve this goal in both software and hardware implementations by exploit the available modern techniques and possibilities in temporal and spatial parallel processing [1]. Gaining high productivity requires devices that are reconfigurable, work in real-time, efficient, low power consumption, and the ability to perform parallel processing features.…”
Section: Introductionmentioning
confidence: 99%
“…This growth requires an exploitation of modern technologies to enhance and increase this processing in a parallelism manner to achieve high throughput. Various algorithms and devices introduced by researchers to achieve this goal in both software and hardware implementations by exploit the available modern techniques and possibilities in temporal and spatial parallel processing [1]. Gaining high productivity requires devices that are reconfigurable, work in real-time, efficient, low power consumption, and the ability to perform parallel processing features.…”
Section: Introductionmentioning
confidence: 99%