Task Scheduling Algorithm for Heterogeneous Real-time Systems Based on Deadline Constraints

Li, Jianpeng; Zheng, Gewei; Zhang, Hanbing; Shi, Guozhen

doi:10.1109/iceiec.2019.8784641

Cited by 11 publications

(3 citation statements)

References 7 publications

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“…Task scheduling process belongs to one of the most important procedures during the designing of the real-time applications as it decides about appropriate and optimal resource utilisation and overall quality of the system [2,[26][27][28][29][30][31][32]. That is why this phase of the contemporary real-time system manufacturing belongs to one of the most crucial issues.…”

Section: Tasks Scheduling Mechanismmentioning

confidence: 99%

“…We can distinguish a lot of techniques and algorithms based on various factors and parameters reflecting properties of a given system or a platform. Techniques operating on a network of heterogeneous processors [26, 29, 30, 32] differentiate the processing cores efficiency. Tasks assignment to resources depends on the processing speed.…”

Section: Tasks Scheduling Mechanismmentioning

confidence: 99%

“…However, that approach cannot be employed in real‐time (predicable) system. The task model similar to ours is analysed in [26], but in our model, the instruction latency and data latency basing on the worst case (WCET) is taken into account. Moreover, in [26] the schedulability of task is based on the evaluation of the margin of time, while we deal with the TFs.…”

Section: Comparison With Other Workmentioning

confidence: 99%

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Flexible hardware approach to multi‐core time‐predictable systems design based on the interleaved pipeline processing

Antolak

Pułka

2020

IET Circuits, Devices & Systems

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The study presents a hardware-based approach to modelling and design of time-predictable electronic embedded systems. It addresses multithread and multitask problems of contemporary real-time systems. Authors propose a universal template of the reconfigurable system architectures that can be flexibly accommodated to a given application. The synthesisable and parametrised model of the system architecture has been implemented in VERILOG. The architecture is based on ARM-like RISC solutions and its heart, the main core, is built of 8-12 stage reconfigurable pipelining with the interleaving mechanism. This core is a basic building block of the system and it can be replicated. Each core can handle several hardware threads with replicated register files. The entire structure has a deadline controlling mechanism that is responsible for tasks' evaluation predictability. The authors analyse the coherency of the proposed memory system and interoperability between hardware threads. Three different static scheduling algorithms have been developed and presented in examples. This study contains the results of the simulation experiments and the summary of the hardware implementation in Virtex-7 FPGA platforms. Authors have investigated the timing parameters of the system and pointed out the areas for further research.

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