This paper presents an approach to use VHDL as input specification to the CAiUAD high-level synthesis system. In particular, it describes a synthesis-oriented compiler which takes a subset of VHDL as input and compiles it into the internal design representatwn of CAIUAD. which can then be synthesized into register-tramfer level design. Since CAMAD supports the design of hardware with concurrency and asynchrony, our VHDL subset includes the concurrent features of the language. We present also in the paper some important conclrcsions concerning how to deal with signals, wait statements, structured data, and subprograms.