TANOR: A Tool for Accelerating N-Body Simulations on Reconfigurable Platform

Kim, J.S.; Mangalagiri, Prasanth; hick, K.; Kandemir, Mahmut; Narayanan, V.; Sobti, K.; Deng, Lanping; Chakrabarti, Chaitali; Pitsianis, Nikos P.; Sun, Xiaobai

doi:10.1109/fpl.2007.4380627

Cited by 6 publications

(4 citation statements)

References 9 publications

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“…FANTOM is an algorithm architecture co-exploration platform for generating fully pipelined hardware accelerators from user-provided MATLAB descriptions [16]. Figure 1 shows the block diagram of the automated design flow in FANTOM.…”

Section: Fantom Toolmentioning

confidence: 99%

“…The two functions are J 0 (x) which is the Bessel function of the first kind with zero order, and e −x which is the exponential function. We use FANTOM tool [16] to generate the HDL of these two functions when implemented in fixed point format. The configuration labeled (n, X, Y) corresponds to the case where n is the degree of Taylor polynomial [21], X is the maximum number of total bits and Y is the maximum number of fraction bits in fixed point implementations.…”

Section: Lookup Table Based Implementationsmentioning

confidence: 99%

“…The models are integrated with FANTOM tool [16], which is an algorithmarchitecture co-design platform for generating fully pipelined hardware accelerators from user-provided MATLAB scripts. By adding the modeling aspect to the FANTOM tool, the system-level designer is provided with fairly accurate hardware-related estimates to guide hardware-software partitioning and even algorithm tuning.…”

Section: Introductionmentioning

confidence: 99%

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Accurate Area, Time and Power Models for FPGA-Based Implementations

Deng

Sobti

Zhang

et al. 2009

J Sign Process Syst

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This paper presents accurate area, time, power estimation models for implementations using FPGAs from the Xilinx Virtex-2Pro family (Deng et al. 2008). These models are designed to facilitate efficient design space exploration in an automated algorithmarchitecture codesign framework. Detailed models for estimating the number of slices, block RAMs and 18 × 18-bit multipliers for fixed point and floating point IP cores have been developed. These models are also utilized to develop power models that consider the effect of logic power, signal power, clock power and I/O power. Timing models have been developed to predict the latency of the fixed point and floating point IP cores. In all cases, the model coefficients have been derived by using curve fitting or regression analysis. The modeling error is quite small for single IP cores; the error for the area estimate, for instance, is on the This paper is an extension of the ICASSP'08 paper "Accurate Models for Estimating Area and Power of FPGA Implementations". average 0.95%. The error for fairly large examples such as floating point implementation of 8-point FFTs is also quite small; it is 1.87% for estimation of number of slices and 3.48% for estimation of power consumption. The proposed models have also been integrated into a hardware-software partitioning tool to facilitate design space exploration under area and time constraints.

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Section: Fantom Toolmentioning

confidence: 99%

Section: Lookup Table Based Implementationsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Accurate Area, Time and Power Models for FPGA-Based Implementations

Deng

Sobti

Zhang

et al. 2009

J Sign Process Syst

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“…We describe in this paper, TANOR, a tool for generating accelerators for numerical computation on reconfigurable platforms [5]. It is intended for computation applications with very large sized data input, and with high accuracy and high throughput requirements.…”

Section: Introductionmentioning

confidence: 99%

An Automated Framework for Accelerating Numerical Algorithms on Reconfigurable Platforms Using Algorithmic/Architectural Optimization

Kim

Deng

Mangalagiri

et al. 2009

IEEE Trans. Comput.

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Abstract-This paper describes TANOR, an automated framework for designing hardware accelerators for numerical computation on reconfigurable platforms. Applications utilizing numerical algorithms on large-size data sets require high-throughput computation platforms. The focus is on N-body interaction problems which have a wide range of applications spanning from astrophysics to molecular dynamics. The TANOR design flow starts with a MATLAB description of a particular interaction function, its parameters, and certain architectural constraints specified through a graphical user interface. Subsequently, TANOR automatically generates a configuration bitstream for a target FPGA along with associated drivers and control software necessary to direct the application from a host PC. Architectural exploration is facilitated through support for fully custom fixed-point and floating point representations in addition to standard number representations such as single precision floating point. Moreover, TANOR enables joint exploration of algorithmic and architectural variations in realizing efficient hardware accelerators. TANOR's capabilities have been demonstrated for three different N-body interaction applications: the calculation of gravitational potential in astrophysics, the diffusion or convolution with Gaussian kernel common in image processing applications, and the force calculation with vector-valued kernel function in molecular dynamics simulation. Experimental results show that TANOR-generated hardware accelerators achieve lower resource utilization without compromising numerical accuracy, in comparison to other existing custom accelerators.

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Accelerating Machine-Learning Algorithms on FPGAs using Pattern-Based Decomposition

Nagarajan

Holland

George

et al. 2009

J Sign Process Syst

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Machine-learning algorithms are employed in a wide variety of applications to extract useful information from data sets, and many are known to suffer from superlinear increases in computational time with increasing data size and number of signals being processed (data dimension). Certain principal machine-learning algorithms are commonly found embedded in larger detection, estimation, or classification operations. Three such principal algorithms are the Parzen window-based, non-parametric estimation of Probability Density Functions (PDFs), K-means clustering and correlation. Because they form an integral part of numerous machine-learning applications, fast and efficient execution of these algorithms is extremely desirable. FPGA-based reconfigurable computing (RC) has been successfully used to accelerate computationally intensive problems in a wide variety of scientific domains to achieve speedup over traditional software implementations. However, this potential benefit is quite often not fully realized because creating efficient FPGA designs is generally carried out in a laborious, case-specific manner requiring a great amount of redundant time and effort. In this paper, an approach using pattern-based decomposition for algorithm acceleration on FPGAs is proposed that offers significant increases in productivity via design reusability. Using this approach, we design, analyze, and implement a multi-dimensional PDF estimation algorithm using Gaussian kernels on FPGAs. First, the algorithm's amenability to a hardware paradigm and expected speedups are predicted. After implementation, actual speedup and performance metrics are compared to the predictions, showing speedup on the order of 20× over a 3.2 GHz processor. Multi-core architectures are developed to further improve performance by scaling the design. Portability of the hardware design across multiple FPGA platforms is also analyzed. After implementing the PDF algorithm, the value of pattern-based decomposition to support reuse is demonstrated by rapid development of the K-means and correlation algorithms.

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TANOR: A Tool for Accelerating N-Body Simulations on Reconfigurable Platform

Cited by 6 publications

References 9 publications

Accurate Area, Time and Power Models for FPGA-Based Implementations

Accurate Area, Time and Power Models for FPGA-Based Implementations

An Automated Framework for Accelerating Numerical Algorithms on Reconfigurable Platforms Using Algorithmic/Architectural Optimization

Accelerating Machine-Learning Algorithms on FPGAs using Pattern-Based Decomposition

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