Tail current flicker noise reduction in LC VCOs by complementary switched biasing

Kassim, A.K.; Sharaf, K.; Ragaie, H.F.

doi:10.1109/icm.2003.238422

Cited by 9 publications

(4 citation statements)

References 6 publications

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“…However, the tail current transistor, MT in Figure 21, is one of the biggest noise contributors of this structure [19]. Different techniques to reduce this noise have been proposed, such as sinusoidal tail current shaping [20], tail current flicker noise reduction by complementary switched biasing [21], sinusoidal shaping of the ISF [22], novel tail current noise second harmonic filtering [23], … A significant and interesting contribution was proposed in 2007 [24] using SOI technology. In fact, the technology was PD (partially depleted) SOI, which allows to suppress the tail current transistor.…”

Section: Comparison With Classical Lc Tank Vcomentioning

confidence: 99%

Section: Comparison With Classical Lc Tank Vcomentioning

confidence: 99%

See 1 more Smart Citation

LC Tank Oscillator Based on New Negative Resistor in FDSOI Technology

Mao,

Charlon,

Leduc

et al. 2024

JLPEA

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Although Moore’s Law reaches its limits, it has never applied to analog and RF circuits. For example, due to the short channel effect (SCE), drain-induced barrier lowering (DIBL), and sub-threshold slope (SS)…, longer transistors are required to implement analog cells. From 22 nm CMOS technology and beyond, for reasons of variability, the channel of the transistors has no longer been doped. Two technologies then emerged: FinFET transistors for digital applications and UTBB FDSOI transistors, suitable for analog and mixed applications. In a previous paper, a new topology was proposed utilizing some advantages of the FDSOI technology. Thanks to this technology, a novel cross-coupled back-gate (BG) technique was implemented to improve analog and mixed signal cells in order to reduce the surface of the integrated circuit. This technique was applied to a current mirror to reduce the small channel effect and to provide high-output impedance. It was demonstrated that it is possible to overcompensate the SCE and DIBL effects and to create a negative output resistor. This paper presents a new LC tank oscillator based on this current mirror functioning as a negative resistor.

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Section: Comparison With Classical Lc Tank Vcomentioning

confidence: 99%

Section: Comparison With Classical Lc Tank Vcomentioning

confidence: 99%

LC Tank Oscillator Based on New Negative Resistor in FDSOI Technology

Mao,

Charlon,

Leduc

et al. 2024

JLPEA

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“…In this case, each tail transistor conducts for half of a sinusoidal cycle. Including this phase noise improvement due to efficient ISF shaping, switching of the tail transistor also reduces its flicker noise, which further improves the oscillator phase noise behavior [7,8]. However, due to the lack of a good model to express the flicker noise and gate-source switching voltage dependency, this effect is not considered here.…”

Section: Noisementioning

confidence: 99%

“…The general phase noise theory developed in [1,2] has introduced a new view to the phase noise of oscillators. On the basis of this theory, some phase noise reduction methods have been proposed [3][4][5][6][7][8]. These methods are based on using symmetric structures and optimizing the oscillator for minimum phase sensitivity.…”

Section: Introductionmentioning

confidence: 99%

Sinusoidal shaping of the ISF in LC oscillators

Jannesari

Kamarei

2007

Circuit Theory & Apps

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SUMMARYA new method to decrease the phase noise of the sinusoidal oscillators is proposed. The proposed method is based on using a dynamic transistor biasing in a typical oscillator topology. This method uses the oscillator impulse sensitivity function (ISF) shaping to reduce the sensitivity of the oscillator to the transistor noise and as a result reducing the oscillator phase noise. A 1.8 GHz, 1.8 V designed oscillator based on the proposed method shows a phase noise of −130.3dBc/Hz at 1 MHz offset frequency, thereby showing about 6 dB phase noise decreasing in comparison with the typical constant bias topology. This result is obtained from the simulation based on 0.18u CMOS technology and on-chip spiral inductor with a quality factor equal to 8.

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