Sinusoidal shaping of the ISF in LC oscillators

SummaryThis study developed a local oscillator (LO) with low phase noise and low power consumption. The proposed oscillator core comprises a pair of cross‐coupled transistors, which are fed by another pair of transistors that injects current at moments close to the peak of output voltage. The position of the current injection transistors, which are inserted in series with the cross‐coupled transistors, affects the waveform of current injected into an inductive–capacitive (LC) tank. Installing a capacitor on the source node of the cross‐coupled transistors increases the current injected into the LC tank and thereby augments the output voltage amplitude and power efficiency of the LO. The resonator phase shift and Q can be corrected by adjusting the source capacitance, which filters noise. These changes reduce the phase noise to −123.4 dBc/Hz at a frequency offset of 1 MHz and improve oscillator performance with a figure of merit equal to −193.5 dBc/Hz. To evaluate the LC tank, a 5 GHz LO was simulated at 1.8 V power supply and 2.5 mW power consumption. The simulation was conducted using a practical 0.18 complementary metal–oxide–semiconductor model manufactured by the Taiwan Semiconductor Manufacturing Company. The simulation results confirmed the analytical findings.

“…Also, on the basis of description above, the tank effective Q is in the maximum value and a new tail current shaping technique reduces the ISF 18,33 …”

Section: Analysis and Design A Low Power And Low Phase Noise Lc Oscilmentioning

confidence: 99%

Increasing power efficiency in the design of a low power and low phase noise CMOS LC oscillator

Kebria

Ghonoodi

2020

“…Description. The phase sensitivity method [89][90][91][92][94][95][96][97][98][99][100][101][102][103][104][105][106][107][108][109][110][111][112] views the oscillator as a system converting (noise) inputs into phase/amplitude (perturbations), as shown in Figure 25. 22 The expression after the '~' symbol more accurately could be given by…”

Section: Procedure/examplementioning

confidence: 99%

“…Various more rigorous techniques more oriented towards computer-aided design (CAD) either solve nonlinear stochastic differential equations (the FPE method) or determine the sensitivity of the oscillator phase to noise at different times during the oscillation cycle [89][90][91][92][94][95][96][97][98][99][100][101][102][103][104][105][106][107][108][109][110][111][112] (Section 4.6). Such methods can predict the phase noise quite accurately, even for hard-switching ring oscillators, but involve complicated mathematics and can be difficult for the practicing engineer to use for circuit analysis or to obtain tractable, closed-form analytical expressions suitable for design intuition or trade-off analysis.…”

Section: Introductionmentioning

confidence: 99%

Survey of integrated‐circuit‐oscillator phase‐noise analysis

Pankratz

Sánchez-Sinencio

2013

This tutorial distills the salient phase-noise analysis concepts and key equations developed over the last 75 years relevant to integrated circuit oscillators. Oscillator phase and amplitude fluctuations have been studied since at least 1938 when Berstein solved the Fokker-Planck equations for the phase/amplitude distributions of a resonant oscillator.The principal contribution of this work is the organized, unified presentation of eclectic phase-noise analysis techniques, facilitating their application to integrated circuit oscillator design. Furthermore, we demonstrate that all these methods boil down to obtaining three things: (1) noise modulation function; (2) noise transfer function; and (3) current-controlled oscillator gain. For each method, this paper provides a short background explanation of the technique, a step-by-step procedure of how to apply the method to hand calculation/computer simulation, and a worked example to demonstrate how to analyze a practical oscillator circuit with that method.This survey article chiefly deals with phase-noise analysis methods, so to restrict its scope, we limit our discussion to the following: (1) analyzing integrated circuit metal-oxide-semiconductor/bipolar junction transistor-based LC, delay, and ring oscillator topologies; (2) considering a few oscillator harmonics in our analysis; (3) analyzing thermal/flicker intrinsic device-noise sources rather than environmental/parametric noise/ wander; (4) providing mainly qualitative amplitude-noise discussions; and (5) omitting measurement methods/phase-noise reduction techniques.We categorize oscillators into one of three varieties, as illustrated in Figure 3: resonant, delay line, or relaxation. First, the resonant oscillator consists of a nonlinear amplifier and a lumped frequencyselective network or resonator, which typically has a band-pass frequency response with a single magnitude peak as indicated conceptually in the figure. This resonator can take the form of an LC tank circuit, dielectric puck, quartz crystal, SAW or bulk acoustic wave transducer, yttrium iron garnet resonator, or ceramic disk resonator to name a few [43,147,148]. IC resonant oscillators typically use LC tanks, although they are often designed to work in concert with an external 874 E. PANKRATZ AND E. SÁNCHEZ-SINENCIO ! ss t ð Þ correspond to the roughly circular trajectory in the figure called a limit cycle [150].Figure 4. Optoelectronic delay-line oscillator. 876 E. PANKRATZ AND E. SÁNCHEZ-SINENCIO For some subtleties of amplitude-noise behavior, see [50,143], where [50] also points out effects of not employing Floquet normalization (cf. Section 4.7).½ =fVoigt ð Þ 2(Gaussian) at small offsets [78,151,152,154]. Chorti also observed that, in general, noise processes with long correlation times tend to create such 'Gaussian' voltage spectra for small frequency offsets f m [151,152]. 4 Note well that, technically, defining spectra for f proves problematic, as it is not stationary and, what is worse, not bounded. This is in fact one reason why the ...

“…Some solutions are presented to overcome these false locks. PLL-based clock and related works can be found in [4][5][6][7][8][9]. In [10], a frequency multiplier uses an edge combiner to generate the output frequency.…”

Section: Introductionmentioning

confidence: 99%

A 120–420 MHz delay‐locked loop with multi‐band voltage‐controlled delay unit

Kuo

Hsu

2012

SUMMARYA low-jitter and low-power dissipation delay-locked loop (DLL) is presented. A proposed multi-band voltage control delay unit (MVCDU) is employed to extend the operation frequency of the DLL by controlling the delay cell within the MVCDU. The jitter of DLL is reduced due to MVCDU's low sensitivity. The delay cell in the MVCDU employs a differential configuration to further reduce the noise impact from the fluctuation in the supply and ground voltage. The operating frequency of the proposed DLL ranges from 120 to 420 MHz. The proposed design has been fabricated in a TSMC 0.18 m CMOS process. The measured RMS and peak-to-peak jitters are 4.86 and 34.55 ps, respectively, at an operating frequency of 300 MHz. The power dissipation is below 14.85 mW at an operating frequency of 420 MHz.