T4: A highly threaded server-on-a-chip with native support for heterogeneous computing

Golla, Robert; Jordan, Paul L.

doi:10.1109/hotchips.2011.7477506

Cited by 7 publications

(3 citation statements)

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“…Accelerators provide as much as three orders of magnitude improvements in compute efficiency over general-purpose processors. Heterogeneous chips combining processors and accelerators already dominate mobile systems [4,2] and are becoming increasingly common in server and desktop systems [17,10]. Large specialized units perform hundreds of operations for each data and instruction fetch, reducing energy waste of programmable cores by two orders of magnitude [20].…”

Section: Introductionmentioning

confidence: 99%

Convolution engine

Qadeer

Hameed

Shacham

et al. 2013

Proceedings of the 40th Annual International Symposium on Computer Architecture

130

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This paper focuses on the trade-off between flexibility and efficiency in specialized computing. We observe that specialized units achieve most of their efficiency gains by tuning data storage and compute structures and their connectivity to the data-flow and datalocality patterns in the kernels. Hence, by identifying key data-flow patterns used in a domain, we can create efficient engines that can be programmed and reused across a wide range of applications.We present an example, the Convolution Engine (CE), specialized for the convolution-like data-flow that is common in computational photography, image processing, and video processing applications. CE achieves energy efficiency by capturing data reuse patterns, eliminating data transfer overheads, and enabling a large number of operations per memory access. We quantify the tradeoffs in efficiency and flexibility and demonstrate that CE is within a factor of 2-3x of the energy and area efficiency of custom units optimized for a single kernel. CE improves energy and area efficiency by 8-15x over a SIMD engine for most applications.

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Section: Introductionmentioning

confidence: 99%

Convolution engine

Qadeer

Hameed

Shacham

et al. 2013

Proceedings of the 40th Annual International Symposium on Computer Architecture

130

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“…To this end, we compared Cobra against two similarly sized designs: a classic CMP comprising 2-wide out-of-order cores and an unoptimized Viper design [18]. We chose the former because it matches the characteristics of modern CMPs [4,10], and the latter because it represents a state-of-the-art distributed architecture. In order to measure Cobra's scalability, we considered systems which can execute 1, 2, 4, 8 and 16 threads, and whose processor logic (caches excluded) occupies 20M, 40M, 80M, 160M and 320M transistors, respectively.…”

Section: Periodic Online Testingmentioning

confidence: 99%

Cobra: A comprehensive bundle-based reliable architecture

Pellegrini

Bertacco

2013

2013 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)

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Abstract-The declining robustness of transistors and their ever-denser integration threatens the dependability of future microprocessors. Classic multicores offer a simple solution to overcome hardware defects: faulty processors can be disabled without affecting the rest of the system. However, this approach becomes quickly an impractical solution at high fault rates.Recently, distributed computer architectures have been proposed to mitigate the effects of faulty transistors by utilizing finegrained hardware reconfiguration, managed by fully decoupled control logic. Unfortunately, such solutions trade flexibility for execution locality, and thus they do not scale to large systems. To overcome this issue we propose Cobra, a distributed, scalable, highly parallel reliable architecture. Cobra is a service-based architecture where groups of dynamic instructions flow independently through the system, making use of the available hardware resources. Cobra organizes the system's units dynamically using a novel resource assignment that preserves locality and limits communication overhead. Our experiments show that Cobra is extremely dependable, and outperforms classic multicores when subjected to 5 or more defects per 100 million transistors. We also show that Cobra operates 80% faster than previous state-of-theart solutions on multi-programmed SPEC CPU2006 workloads and it improves cache hit rate by up to 62%. Our runtime fault detection techniques have a performance impact of only 3%.

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“…The design of putting a number of identical single-issue or dual-issue IO cores onto a single chip has been adopted by many classic products, such as the Raw processor [33], the Tilera processor [115], the UltraSPARC T1/T2 processor [116], the Larrabee processor [117], and the OCTEON processor [118]. More recently, Intel announces its MIC architecture [119], which follows the same design direction.…”

Section: Architecturesmentioning

confidence: 99%

Trace-Based Dynamic Binary Parallelization

Yang¹

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With the number of cores increasing rapidly but the performance per core increasing slowly at best, software must be parallelized in order to improve performance. Manual parallelization is often prohibitively time-consuming and error-prone (especially due to data races and memory-consistency complexities), and some portions of code may simply be too difficult to understand or refactor for parallelization. Most existing automatic parallelization techniques are performed statically at compile time and require source code to be analyzed, leaving a large fraction of software behind.In many cases, some or all of the source code and development tool chain is lost or, in the case of third-party software, was never available. Furthermore, modern applications are assembled and defined at run time, making use of shared libraries, virtual functions, plugins, dynamically-generated code, and other dynamic mechanisms, as well as multiple languages. All these aspects of separate compilation prevent the compiler from obtaining a holistic view of the program, leading to the risk of incompatible parallelization techniques, subtle data races, and resource over-subscription. All the above considerations motivate dynamic binary parallelization (DBP).This dissertation explores the novel idea of trace-based DBP, which provides a large instruction window without introducing spurious dependencies. We hypothesize that traces provide a generally good trade-off between code visibility and analysis accuracy for a wide variety of applications so as to achieve better parallel performance. Compared to the raw dynamic instruction stream (DIS), traces expose more distant parallelism opportunities because their average length is typically much larger than the size of the hardware instruction window. Compared to the complete control flow graph (CFG), traces only contain control and data dependencies on the execution path which is actually taken. More importantly, while DIS-based DBP typically only exploits fine-grained parallelism and CFG-based DBP typically only exploits coarse-grained parallelism, traces can be used as a unified representation of program execution to seamlessly incorporate the exploitation of both coarse-and fine-grained parallelism.We develop Tracy, an innovative DBP framework which monitors a program at run time and i Abstract ii dynamically identifies hot traces, parallelizes them, and caches them for later use so that the program can run in parallel every time a hot trace repeats. Our experimental results have demonstrated that for floating point benchmarks, Tracy can achieve an average speedup of 2.16x, 1.51x better than the speedup achieved by Core Fusion, one representative of DIS-based DBP techniques. Although the average speedup achieved by Tracy is only 1.04x better than the speedup achieved by CFG-based DBP, Tracy can speed up all floating point benchmarks while CFG-based DBP fails to parallelize three out of eight applications at all. The performance of Tracy is not always better than the performance of exist...

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T4: A highly threaded server-on-a-chip with native support for heterogeneous computing

Cited by 7 publications

References 0 publications

Convolution engine

Convolution engine

Cobra: A comprehensive bundle-based reliable architecture

Trace-Based Dynamic Binary Parallelization

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