Systolic Array Implementation of Mix Column and Inverse Mix Column of AES

Sasikumar, Midhun; Sreehari, K N; Bhakthavatchalu, Ramesh

doi:10.1109/iccsp.2019.8697927

Cited by 2 publications

(1 citation statement)

References 4 publications

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“…In hardware encryption, a customized processor handles the entire process of encryption, decryption and access to protect data [32]- [34]. Additional components are not required for encryption process as the device comprises of the required utilities.…”

Section: Hardware Encryptionmentioning

confidence: 99%

Modified Blockchain based Hardware Paradigm for Data Provenance in Academia

Devika¹,

Bhakthavatchalu²

2021

Adv. sci. technol. eng. syst. j.

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Educational organizations often need to distribute academic transcripts and certificates upon student's request since they are mandatory for admission into new scholarly programs including placement activities. Manual procedures involved with the transmission process of academic document is indeed a tedious task that results in substantial overhead. Thus the necessity for an autonomous electronic system for transfer of records among institutions is on the verge. This paper discuss and portray a hardware approach on the cryptographic elements of blockchain to impart data security and privacy that are found inadequate in its software counterpart.The novelty of this work relies on the design and implementation of a hardware equivalent structure for blockchain which could greatly alleviate the chances of various software attacks and security breach in existence. The solution proposed could cut down the waiting period of students to transmit their credentials and in addition provide a trustworthy verification platform to elude academic deceit. It can be integrated along with existing permission based blockchain framework to form a conjoined hardware-software architecture.

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Section: Hardware Encryptionmentioning

confidence: 99%