Systematic Analysis of Energy and Delay Impact of Very Deep Submicron Process Variability Effects in Embedded SRAM Modules

Wang, Hua; Miranda, M.; Dehaene, Wim; Catthoor, Francky; Maex, Karen

doi:10.1109/date.2005.291

Cited by 16 publications

(3 citation statements)

References 12 publications

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“…However, as the geometries of the transistors reach the physical limits of operation, it becomes increasingly difficult for the hardware components to achieve reliable operation. The variability in process technology, the issue of thermal hotspots and the effect of various noise sources, such as power supply fluctuations, pose major challenges for the reliable operation of current and future MPSoCs [33], [1]. Failures may be temporary (for example if due to thermal effects) or permanent.…”

Section: Introductionmentioning

confidence: 99%

“…Failures may be temporary (for example if due to thermal effects) or permanent. Key MPSoC components that are affected by sub-micron technology issues are the on-chip memories [33], where errors can flip the stored bits, possibly resulting in a complete system failure. Current memories already include extensive mechanisms to tolerate single-bit errors, e.g.…”

Section: Introductionmentioning

confidence: 99%

“…errorcorrecting codes such as Hamming codes [34], [13]. However these mechanisms are expensive and the overhead in area, power and delay to recover from multi-bit errors would be very high [33]. Hence, with the increasing uncertainty of device operation, an effective system-level support to memory fault tolerance will be mandatory to ensure proper functionality at a reasonable cost.…”

Section: Introductionmentioning

confidence: 99%

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Reliability Support for On-Chip Memories Using Networks-on-Chip

Angiolini

Atienza²,

Murali

et al. 2006

2006 International Conference on Computer Design

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As the geometries of the transistors reach the physical limits of operation, one of the main design challenges of Systems-on-Chips (SoCs) will be to provide dynamic (run-time) support against permanent and intermittent faults that can occur in the system. One of the most critical elements that affect the correct behavior of the system is the unreliable operation of onchip memories. In this paper we present a novel solution to enable fault tolerant on-chip memory design at the system level for multimedia applications, based on the Network-on-Chip (NoC) interconnection paradigm. We transparently keep backup copies of critical data on a reliable memory; upon a fault event, data is fetched from the backup copy in hardware, without any software intervention. The use of a NoC backbone enables an efficient design which is modular, scalable and efficient. We proceed to demonstrating its effectiveness with two real-life application case studies, and explore the performance under varying architectural configurations. The overhead to support the proposed approach is very small compared to non-fault tolerant systems, i.e. no negative performance impact and an area increase dominated by that of just the backup storage itself.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Reliability Support for On-Chip Memories Using Networks-on-Chip

Angiolini

Atienza²,

Murali

et al. 2006

2006 International Conference on Computer Design

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System-level process variability compensation on memory organizations. On the scalability of multi-mode memories

Sanz¹,

Prieto²,

Papanikolaou³

et al. 2009

2009 Asia and South Pacific Design Automation Conference

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BTI impact on logical gates in nano-scale CMOS technology

Khan

Hamdioui

Kükner³

et al. 2012

2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits &Amp; Systems (DDECS)

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Abstract-As semiconductor manufacturing has entered into the nanoscale era, Bias Temperature Instability (BTI) -Negative BTI (NBTI) in PMOS transistors and Positive BTI (PBTI) in NMOS transistors-has become one of the most serious aging mechanisms that reduces reliability of logic gates. This paper presents a simulation-based BTI analysis in both basic (such as NAND and NOR) and complex gates while considering the impact of input's duty cycle, the frequency at which they change, as well as the impact of the stressed transistor location. The simulation results show that the impact of BTI is strongly gate dependent and that in general the impact in complex gates is larger. When considering both NBTI and PBTI for basic gates, the results reveal that for a NOR gate the impact of NBTI is 2.19× higher than that of PBTI; while for a NAND gate, PBTI impact is 1.27× higher than that of NBTI. When considering different input duty cycles and their frequencies, the results show that the higher the duty cycle, the lower NBTI impact and the higher the PBTI impact regardless of the gate types and the frequency; a variation of ±30% duty cycle causes a variation of up to 49% variation in the impact of NBTI and a variation of 16% in the impact of PBTI. For complex gates, the results show similar trends, but with higher impact.

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Systematic Analysis of Energy and Delay Impact of Very Deep Submicron Process Variability Effects in Embedded SRAM Modules

Abstract: Variability is becoming a serious problem in process

Cited by 16 publications

References 12 publications

Reliability Support for On-Chip Memories Using Networks-on-Chip

Reliability Support for On-Chip Memories Using Networks-on-Chip

System-level process variability compensation on memory organizations. On the scalability of multi-mode memories

BTI impact on logical gates in nano-scale CMOS technology

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