System verification using multilevel concurrent simulation

Lentz, K.P.; Heller, J.; Montessoro, Pier Luca

doi:10.1109/40.748797

Cited by 3 publications

(1 citation statement)

References 19 publications

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“…The test bench (TB) works by contrasting the outcomes from the two FPGA models which both get a similar input i/p stimulus and after that errors any disparities that are found. The genuine power in this strategy is that when a mistake is discovered you can test into the two models and follow signs to perceive what is causing the issue [17] 2) Generate a downstream traceability to ensure that each FPGA requirement is fully implemented by an HDL function. FPGA designers must create additional functions as needed to fully implement each FPGA requirement.…”

Section: B Developing Acceptance Coverage By Testmentioning

confidence: 99%

An Approach for Generating the Self-Checking Test-Bench

Nanda¹

2018

IJRASET

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To verify the complex functionalities for an IP core or testing of critical IP core under module level testing giving more complexity at the time of simulation to analysis the output at accurate level due this fact, the engineer takes more time to finalize the outputs at different level. Due to that, the complexity of IP core at market level gets down. Complex critical functionalities and to verify the IP core as per Do-254, in any case, confirmation of necessities by test during board testing is challenging and time-consuming in some cases like normal, boundary and robustness test benches. This paper clarifies the critical functionalities with one of technique i.e. self checking test bench, and gives proposals how to beat them. The efficiency of the self-checking test bench is demonstrated with FIFO as case study.

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Section: B Developing Acceptance Coverage By Testmentioning

confidence: 99%

An Approach for Generating the Self-Checking Test-Bench

Nanda¹

2018

IJRASET

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TUFTsim: a multiple domain simulator for experimentation

Heller

Lentz

Proceedings 32nd Annual Simulation Symposium

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How to bridge the gap between simulation and test

Zambaldi

Ecker

2004 International Conferce on Test

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The Tester-Related Simulation Environment (TRSE) and applied methodology dose the gap befween physical test and simulation. Simulation checks the correctness of the implementation with respect to the specification, and test checks the correctness of the fabricated product with respect to the implementation. Unfortunately, simulation and test are still not connected in a smooth verification flow. Test cases and stimuli from simulation cannot be direct/y used for test. They may be used only in a restricted way, and affer some adaptation. The approach presented here allows a better reuse of simulation stimuli for test issues. The main idea consists of inserting a special simulation element (SE) called a "transforming SE". This transforming SE is responsible for the adaptation and single cyde relation of the paftem. It also traces the interface pattem for direct use on a tester. These patterns are finally used for deriving test programs from functional paffems and for providing paftems for an e-beam analysis of the manufactured chip. The second main feature of the TRSE is the connection of each SE with an appropriate reference clock. This enables the SE to provide both synchronous and asynchronous communication with the unit under verification (UUVJ.Both the modeling of a test case and general methodology issues have a big influence in how easily a paftern can be adapted for the tester. Some practical modeling and methodology hints are given.

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System verification using multilevel concurrent simulation

Cited by 3 publications

References 19 publications

An Approach for Generating the Self-Checking Test-Bench

An Approach for Generating the Self-Checking Test-Bench

TUFTsim: a multiple domain simulator for experimentation

How to bridge the gap between simulation and test

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