System-On-Chip for Biologically Inspired Vision Applications

Abstract

Neuromorphic vision algorithms are biologically-inspired computational models of the primate visual pathway. They promise robustness, high accuracy, and high energy efficiency in advanced image processing applications. Despite these potential benefits, the realization of neuromorphic algorithms typically exhibit low performance even when executed on multi-core CPU and GPU platforms. This is due to the disparity in the computational modalities prominent in these algorithms and those modalities most exploited in contemporary computer architectures. In essence, acceleration of neuromorphic algorithms requires adherence to specific computational and communicational requirements. This paper discusses these requirements and proposes a framework for mapping neuromorphic vision applications on a System-on-Chip, SoC. A neuromorphic object detection and recognition on a multi-FPGA platform is presented with performance and power efficiency comparisons to CMP and GPU implementations.

Modification and hardware implementation of cortex‐like object recognition model

“…In some papers, e.g. [13, 15, 17], the normalised dot product (NDP) is also used instead of (5). In both forms of the above calculations, 256 multiply accumulates (MACs) are needed for attaining the Euclidean distance of 16 × 16 patches in every location and orientation of the C1 layer's outputs.…”

Dynamically reconfigurable AES cryptographic core for small, power limited mobile sensors

“…Section III introduces the system architecture for the proposed FPGA-based AES coprocessor. Section IV describes the implementation details of the reconfigurable AES engine, followed by an overview of the Vortex data router [15,16,17,18] in Section V. Section VI describes the resource performance controller of our design. Workflow simulations are presented in Section VII, followed by performance validation and tradeoff analysis in Section VIII.…”

He-P2012: Performance and Energy Exploration of Architecturally Heterogeneous Many-Cores

“…This approach has been leveraged for software-defined radio applications (see for example Ramacher et al [37], CEA MAGALI [9,23] and StepNP [31]), in high-performance computing (for example by Maxeler [33]) and in the embedded vision domain (for example Vortex [29,40] for biologically-inspired vision acceleration, and NeuFlow [19] and nn-X [20], which focus on Convolutional Neural Network acceleration). Loose coupling of processors and accelerators through messagepassing channels is extremely scalable and power-efficient, as accelerators completely bypass the Von Neumann bottleneck, working only when they are fed with input.…”