System-on-a-chip cosimulation and compilation

Liem, Clifford; Nacabal, F.; Valderrama, Carlos; Paulin, Pierre; Jerraya, Ahmed

doi:10.1109/54.587736

Cited by 37 publications

(27 citation statements)

References 8 publications

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“…Only a handful of years ago, it was easy enough to hook a probe to the memory and I/O buses, but, with the advent of systems on a chip and application-specific integrated circuits, it is no longer possible to obtain those signals for they never leave the silicon [27], [35]. The only way to debug these systems is to either probe the silicon itself (a bit unrealistic) or to add logic to the chip to bring the desired signal off the chip; the latter option is limited by the number of physical pins that can be put on a chip and spared for simple debug and evaluation purposes.…”

Section: Motivationmentioning

confidence: 99%

The performance and energy consumption of embedded real-time operating systems

Baynes

Collins

Fiterman³

et al. 2003

IEEE Trans. Comput.

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Abstract-This paper presents the modeling of embedded systems with SimBed, an execution-driven simulation testbed that measures the execution behavior and power consumption of embedded applications and RTOSs by executing them on an accurate architectural model of a microcontroller with simulated real-time stimuli. We briefly describe the simulation environment and present a study that compares three RTOSs: C/OS-II, a popular public-domain embedded real-time operating system; Echidna, a sophisticated, industrial-strength (commercial) RTOS; and NOS, a bare-bones multirate task scheduler reminiscent of typical "roll-your-own" RTOSs found in many commercial embedded systems. The microcontroller simulated in this study is the Motorola M-CORE processor: a low-power, 32-bit CPU core with 16-bit instructions, running at 20MHz. Our simulations show what happens when RTOSs are pushed beyond their limits and they depict situations in which unexpected interrupts or unaccounted-for task invocations disrupt timing, even when the CPU is lightly loaded. In general, there appears no clear winner in timing accuracy between preemptive systems and cooperative systems. The power-consumption measurements show that RTOS overhead is a factor of two to four higher than it needs to be, compared to the energy consumption of the minimal scheduler. In addition, poorly designed idle loops can cause the system to double its energy consumption-energy that could be saved by a simple hardware sleep mechanism.

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Section: Motivationmentioning

confidence: 99%

The performance and energy consumption of embedded real-time operating systems

Baynes

Collins

Fiterman³

et al. 2003

IEEE Trans. Comput.

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“…C-VHDL (or Verilog) environments can be developed [18]. Most commercial HDL simulators support the execution of external C functions for this purpose.…”

Section: Related Workmentioning

confidence: 99%

RTOS modeling in SystemC for real-time embedded SW simulation: A POSIX model

Posadas

Ádamez

Villar

et al. 2005

Des Autom Embed Syst

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SystemC is committed to support the requirements for an integrated, HW/SW codesign flow, thus allowing the development of complex, multiprocessing, Systems-on Chip (MpSoC). To make this possible, efficient modeling and simulation methodologies for RealTime, Embedded (RT/E) SW in SystemC have to be developed, so that the designer can verify and refine the application SW together with the rest of the elements of the platform. Accurate modeling of the application SW requires an accurate model of the RTOS. Nevertheless, low-level, dynamic timing characteristics of the RTOS such as time-slicing, priority-based preemptive scheduling, interrupts and exceptions do not have a direct implementation in SystemC.In this paper, techniques are proposed to accurately model the detailed RTOS functionality on top of the SystemC execution kernel. The model allows timed-simulation and refinement of the RT/E SW code in SystemC. The simulation technology has been applied to the development of a high-level, POSIX simulation library in SystemC. The library allows the designer a fast, sufficiently accurate, timed simulation of the application SW running on top of POSIX. As most current RTOSs support this standard, the library is portable to different development frameworks. The library provides the required infrastructure for a complete, H. Posadas ( ) .

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“…Nevertheless they are adequate just in the very first stage of the development, before the HW/SW partitioning, because the HW and SW design flows need different techniques and different tools when the abstraction level decreases toward a real implementation. [3][4][5][6] use distinct simulation engines and different language descriptions for the hardware and the software side. This allows to use levels of abstraction lower than the behavioral one, and to evaluate the software in its compiled (binary code) form.…”

Section: Co-simulation Environmentsmentioning

confidence: 99%

SystemC co-simulation for core-based embedded systems

Fummi

Loghi

Perbellini

et al. 2007

Des Autom Embed Syst

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SystemC is becoming the reference language for hardware description in EDA community. It is suitable for describing hardware at several abstraction levels, and it can be used to develop devices for programmable, CPU-based, systems. In such a context, there are several requirements to meet. The hardware under development can be an extension module for an existing system, possibly with no knowledge on the actual system implementation. At the same time, the module to develop can be minded as a CPU-independent device that should be evaluated against different processors. Hence, the developer should leverage different techniques, depending on the development environment involved.We present a framework that allows to co-simulate the hardware under development and the software, in a system extending context as well as in a CPU-centered design. Such a framework can use different abstraction levels for the hardware, thus allowing to meet the best accuracy/performance tradeoffs. Moreover, when required, the CPU can be replaced on the fly, keeping the software portion just marginally changed (or not modified at all), then realizing the required modularity of the design.

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System-on-a-chip cosimulation and compilation

Cited by 37 publications

References 8 publications

The performance and energy consumption of embedded real-time operating systems

The performance and energy consumption of embedded real-time operating systems

RTOS modeling in SystemC for real-time embedded SW simulation: A POSIX model

SystemC co-simulation for core-based embedded systems

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