System-level parallelism and concurrency maximisation in reconfigurable computing applications

González

ACM Trans. Reconfigurable Technol. Syst.

2009

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Runtime Reconfiguration (RTR) has been traditionally utilized as a means for exploiting the flexibility of High-Performance Reconfigurable Computers (HPRCs). However, the RTR feature comes with the cost of high configuration overhead which might negatively impact the overall performance. Currently, modern FPGAs have more advanced mechanisms for reducing the configuration overheads, particularly Partial Runtime Reconfiguration (PRTR). It has been perceived that PRTR on HPRC systems can be the trend for improving the performance. In this work, we will investigate the potential of PRTR on HPRC by formally analyzing the execution model and experimentally verifying our analytical findings by enabling PRTR for the first time, to the best of our knowledge, on one of the current HPRC systems, Cray XD1. Our approach is general and can be applied to any of the available HPRC systems. The paper will conclude with recommendations and conditions, based on our conceptual and experimental work, for the optimal utilization of PRTR as well as possible future usage in HPRC.

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Section: Execution Model Formulationmentioning

confidence: 99%

Exploiting Partial Runtime Reconfiguration for High-Performance Reconfigurable Computing

González

ACM Trans. Reconfigurable Technol. Syst.

2009

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“…In addition, it will help us gain in-depth insight about the boundaries and/or conditions for performance gain. In achieving this objective, we will follow an approach in the derivation of the model similar to what has been proposed in [16,19,20,21,22,23].…”

Section: Execution Model Formulationmentioning

confidence: 99%

“…The execution cycle for any task on an HPRC consists of the computations time, the total I/O time and the configuration time [16,19,20], as shown in Fig. 2.…”

Section: A Analysismentioning

confidence: 99%

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Virtualizing and sharing reconfigurable resources in High-Performance Reconfigurable Computing systems

González

2008 Second International Workshop on High-Performance Reconfigurable Computing Technology and Applications

2008

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High-PerformanceReconfigurable Computers (HPRCs) are parallel computers but with added FPGA chips. Examples of such systems are the Cray XT5 h and Cray XD1, the SRC-7 and SRC-6, and the SGI Altix/RASC. The execution of parallel applications on HPRCs mainly follows the SingleProgram Multiple-Data (SPMD) model, which is largely the case in traditional High-Performance Computers (HPCs). In addition, the prevailing usage of FPGAs in such systems has been as coprocessors. The overall system resources, however, are often underutilized because of the asymmetric distribution of the reconfigurable processors relative to the conventional processors. This asymmetry is often a challenge for using the SPMD programming model on these systems. In this work, we propose a resource virtualization solution based on Partial Run-Time Reconfiguration (PRTR). This technique will allow sharing the reconfigurable processors among the underutilized processors. We will present our virtualization infrastructure augmented with an analytical investigation. We will verify our proposed concepts with experimental implementations using the Cray XD1 as a testbed. It will be shown that this approach is quite promising and will allow full exploitation of the system resources with fair sharing of the reconfigurable processors among the microprocessors. Our approach is general and can be applied to any of the available HPRC systems.

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A system-level design methodology for reconfigurable computing applications

Proceedings. 2005 IEEE International Conference on Field-Programmable Technology, 2005.

Gaj