System level jitter characterization of high speed I/O systems

Oh, Dan

doi:10.1109/isemc.2012.6351789

Cited by 15 publications

(2 citation statements)

References 6 publications

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“…Much work has been focused on interface (IO) designs where timing jitter is a crucial part of the overall system performance. Proper modeling of PSIJ can lead to reduction in PDN requirements; for example, in clock forwarding architecture, the impact of jitter is drastically reduced due to jitter tracking between data and clock signals [5]. Unfortunately, no major work has been performed to analyze timing jitter for core logic blocks.…”

Section: Introductionmentioning

confidence: 99%

Power integrity analysis for core logic blocks

Razmadze

Chandrasekar

2013

2013 IEEE 22nd Conference on Electrical Performance of Electronic Packaging and Systems

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In this paper, the new framework for power integrity analysis for core logic blocks is presented. Balancing on-chip timing budget becomes more challenging as both data and clock jitter increase due to large power noise. Conventional power integrity (PI) analysis focuses on reducing supply noise and does not provide timing jitter information. This paper proposes a general framework to model timing jitter due to supply noise. The proposed methodology can be used to define power distribution network (PDN) design requirements. This timingbased PDN design leads to significant reduction in the pessimism associated with either conventional target impedance concept, or static or dynamic power integrity analysis.

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Section: Introductionmentioning

confidence: 99%

Power integrity analysis for core logic blocks

Razmadze

Chandrasekar

2013

2013 IEEE 22nd Conference on Electrical Performance of Electronic Packaging and Systems

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“…For this reason, an equivalent circuit or parametric behavioral modelling, which are generated under the above V-t conditions, will not accurately predict the predriver’s output timing distortions, which are the input of the last-stage driver model. Moreover, this shortcoming limits the usage of the behavioral models when they are subjected to supply ripple voltage derived from frequency domain simulations [ 8 , 9 , 10 , 11 , 12 ].…”

Section: Introductionmentioning

confidence: 99%

Neural-Network Based Modeling of I/O Buffer Predriver under Power/Ground Supply Voltage Variations

Souilem

Tripathi

Melício

et al. 2021

Sensors

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This paper presents a neural-network based nonlinear behavioral modelling of I/O buffer that accounts for timing distortion introduced by nonlinear switching behavior of the predriver electrical circuit under power and ground supply voltage (PGSV) variations. Model structure and I/O device characterization along with extraction procedure were described. The last stage of the I/O buffer is modelled as nonlinear current-voltage (I-V) and capacitance voltage (C-V) functions capturing the nonlinear dynamic impedances of the pull-up and pull-down transistors. The mathematical model structure of the predriver was derived from the analysis of the large-signal electrical circuit switching behavior. Accordingly, a generic and surrogate multilayer neural network (NN) structure was considered in this work. Timing series data which reflects the nonlinear switching behavior of the multistage predriver’s circuit PGSV variations, were used to train the NN model. The proposed model was implemented in the time-domain solver and validated against the reference transistor level (TL) model and the state-of-the-art input-output buffer information specification (IBIS) behavioral model under different scenarios. The analysis of jitter was performed using the eye diagrams plotted at different metrics values.

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A Thomas Algorithm-Based Generic Approach for Modeling of Power Supply Induced Jitter in CMOS Buffers

et al. 2019

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This paper presents an efficient and generic method for analysis of power supply induced jitter (PSIJ) in a chain of CMOS inverters as well as tapered buffers due to multiple deterministic noise sources. Generalised semi-analytical relations between noise and PSIJ are developed using Thomas algorithm. The proposed analysis can be used for both cases of same size of inverters as well as tapered buffers, and also for considering the effect of on-chip and off-chip interconnects. The validity and the efficiency of the proposed modeling is demonstrated for various applications of chain of inverters such as buffers in clock distribution, delay locked loops and I/Os, etc. INDEX TERMS CMOS inverter, chain of inverters, clock-network, delay-line, I/O, jitter, power supply noise, power supply induced jitter, time interval error, tapered buffer. APPENDIX C FORMULATION OF TRI-DIAGONAL MATRIX FOR EXAMPLE-3

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System level jitter characterization of high speed I/O systems

Cited by 15 publications

References 6 publications

Power integrity analysis for core logic blocks

Power integrity analysis for core logic blocks

Neural-Network Based Modeling of I/O Buffer Predriver under Power/Ground Supply Voltage Variations

A Thomas Algorithm-Based Generic Approach for Modeling of Power Supply Induced Jitter in CMOS Buffers

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