System integration of tightly-coupled processor arrays using reconfigurable buffer structures

Abstract

As data locality is a key factor for the acceleration of loop programs on processor arrays, we propose a buffer architecture that can be configured at run-time to select between different schemes for memory access. In addition to traditional address-based memory banks, the buffer architecture can deliver data in a streaming manner to the processing elements of the array, which supports dense and sparse stencil operations. Moreover, to minimize data transfers to the buffers, the design contains an interlinked mode, which is especially targeted at 2-D kernel computations. The buffers can be used individually to achieve high data throughput by utilizing a maximum number of I/O channels to the array, or concatenated to provide higher storage capacity at a reduced amount of I/O channels.

*‐Predictable MPSoC execution of real‐time control applications using invasive computing

“…Data transfer between the global memory and the PE array is only performed through the PEs at the border of the array, which is connected to a set of surrounding RBs. These buffers can be configured, to either work as simple FIFOs or as RAM‐based addressable memory banks 34 . The AGs generate the correct sequence of read/write accesses according to a given loop schedule, and they work in parallel with the main computational units or processors to ensure efficient storage/feed of data to/from the main memory.…”

Reconfigurable Buffer Structures for Coarse-Grained Reconfigurable Arrays

“…Although this solution scales very well, the overhead for accessing shared resources may compromise the performance of such accelerators. As a solution for this challenge, we propose to use a very flexible buffer structure that can be configured at runtime either as addressable RAM or pixel buffer as first presented in [3].…”

“…In this paper, we propose to use such buffers for coupling a RISC processor directly to the border processing elements of a class of CGRAs called TCPAs (tightly coupled processor arrays [3]). We are using an edge detection algorithm as a case study to demonstrate how the image processing throughput can thereby be increased up to the memory bandwidth available in the system.…”

“…In (a), (b), and (c), a reconfigurable I/O buffer architecture is shown which may be configured into different modes and trade-off the buffer sizes with the number of available independent ports to the processor array[3].…”