Synthesis of synchronous sequential logic circuits from partial input/output sequences

Improvements in FSM Evolutions from Partial Input/Output Sequences

“…Ref. [2] gives an approximation formula to estimate the length of the TSs that yields a correct FSM, based on the waiting times in sampling problem solution [10].…”

“…The task of modeling existing systems by exclusively observing their input/output (I/O) behavior is of interest when the purpose is (1) to uncover the states of natural systems, (2) to model synthetic systems implemented from scratch, in an ad hoc manner or for which the documentation has been lost and (3) to generate automata from scenario (trace) specifications, a fruitful area in the telecommunications domain. At present, most of these problems are outside the scope of conventional techniques.…”

“…More recent attempts have been successful in synthesizing sequential systems with the aid of Genetic Algorithms (GAs) [2,3,4]. In [1] an approach to synthesize synchronous sequential logic circuits from partial I/O sequences by using technologybased representation (a netlist of gates and flip-flops) is presented.…”

Extrinsic Evolution of Finite State Machine

“…One of the advantages of EHW is that if hardware errors occur or a new hardware functionality is required, EHW can alter its own hardware structure in order to accommodate such changes. EHW approach has begun to show that it is possible to evolve sequential logic circuits in a radically different way [8,9,10]. Thus, it has been proposed that the design of sequential logic circuit can be obtained using entirely only evolvable hardware [3].…”

“…Higuchi et al have successfully evolved such sequential logic circuits as 4-state machine, 3-bit counter. It has been appeared only one more approach that attempted to evolve sequential logic circuits from the partial input/output sequence [8,11]. The circuits evolved include reversible 8-counter, reversible 4-counter, modulo-4 counter, 0101 detector, 1010 detector, serial adder [12].…”