Synthesis of Platform Architectures from OpenCL Programs

Owaida, Muhsen; Bellas, Nikolaos; Daloukas, Konstantis; Antonopoulos, Christos D.

doi:10.1109/fccm.2011.19

Cited by 69 publications

(48 citation statements)

References 8 publications

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“…Both Altera [16] and Xilinx [17] provide tools to implement OpenCL-compliant applications in their hardware platforms. Hence, researchers from academia have also put their effort in working with OpenCL in order to generate custom accelerators, with tools such as SOpenCL [18], methodologies based upon commercial tools [19] or by using LLVM to accelerate synthesis processes [20].…”

Section: Related Workmentioning

confidence: 99%

Design of OpenCL-compatible multithreaded hardware accelerators with dynamic support for embedded FPGAs

Rodríguez

Valverde

Torre

2015

2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig)

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Abstract-ARTICo3 is an architecture that permits to dynamically set an arbitrary number of reconfigurable hardware accelerators, each containing a given number of threads fixed at design time according to High Level Synthesis constraints. However, the replication of these modules can be decided at runtime to accelerate kernels by increasing the overall number of threads, add modular redundancy to increase fault tolerance, or any combination of the previous. An execution scheduler is used at kernel invocation to deliver the appropriate data transfers, optimizing memory transactions, and sequencing or parallelizing execution according to the configuration specified by the resource manager of the architecture. The model of computation is compatible with the OpenCL kernel execution model, and memory transfers and architecture are arranged to match the same optimization criteria as for kernel execution in GPU architectures but, differently to other approaches, with dynamic hardware execution support.In this paper, a novel design methodology for multithreaded hardware accelerators is presented. The proposed framework provides OpenCL compatibility by implementing a memory model based on shared memory between host and compute device, which removes the overhead imposed by data transferences at global memory level, and local memories inside each accelerator, i.e. compute unit, which are connected to global memory through optimized DMA links. These local memories provide unified access, i.e. a continuous memory map, from the host side, but are divided in a configurable number of independent banks (to increase available ports) from the processing elements side to fully exploit data-level parallelism. Experimental results show OpenCL model compliance using multithreaded hardware accelerators and enhanced dynamic adaptation capabilities.

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Section: Related Workmentioning

confidence: 99%

Design of OpenCL-compatible multithreaded hardware accelerators with dynamic support for embedded FPGAs

Rodríguez

Valverde

Torre

2015

2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig)

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“…We used the SOpenCL tool [6] to automatically generate hardware accelerators starting from an OpenCL LDPC decoder code. SOpenCL allows to quickly explore different architectural scenarios and evaluate the quality of the design in terms of computational bandwidth, clock frequency and size.…”

Section: B Fpgas 1) Sopencl Backgroundmentioning

confidence: 99%

“…OpenCL allows developing parallel kernels that are portable across several multicore platforms and that permit achieving good cross-platform performance levels [5]. Recent extensions to OpenCL also allow to transparently mapping algorithms to FPGAs [6]. This motivates the choice made in the paper to adopt such common and generic programming model to support simulation setups for a variety of parallel computing platforms.…”

Section: Introductionmentioning

confidence: 99%

Shortening Design Time through Multiplatform Simulations with a Portable OpenCL Golden-model: The LDPC Decoder Case

Falcão

Owaida

Novo

et al. 2012

2012 IEEE 20th International Symposium on Field-Programmable Custom Computing Machines

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Abstract-Hardware designers and engineers typically need to explore a multi-parametric design space in order to find the best configuration for their designs using simulations that can take weeks to months to complete. For example, designers of special purpose chips need to explore parameters such as the optimal bitwidth and data representation. This is the case for the development of complex algorithms such as Low-Density Parity-Check (LDPC) decoders used in modern communication systems. Currently, high-performance computing offers a wide set of acceleration options, that range from multicore CPUs to graphics processing units (GPUs) and FPGAs. Depending on the simulation requirements, the ideal architecture to use can vary. In this paper we propose a new design flow based on OpenCL, a unified multiplatform programming model, which accelerates LDPC decoding simulations, thereby significantly reducing architectural exploration and design time. OpenCL-based parallel kernels are used without modifications or code tuning on multicore CPUs, GPUs and FPGAs. We use SOpenCL (Silicon to OpenCL), a tool that automatically converts OpenCL kernels to RTL for mapping the simulations into FPGAs. To the best of our knowledge, this is the first time that a single, unmodified OpenCL code is used to target those three different platforms. We show that, depending on the design parameters to be explored in the simulation, on the dimension and phase of the design, the GPU or the FPGA may suit different purposes more conveniently, providing different acceleration factors. For example, although simulations can typically execute more than 3× faster on FPGAs than on GPUs, the overhead of circuit synthesis often outweighs the benefits of FPGA-accelerated execution.

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“…And it can also be mapped to general purpose CPUs efficiently [23]. Recent studies attempt to use OpenCL for more diverging target architectures, such as FPGA [18] and ASIP [21]. In [10], She et al proposed OpenCL code generation for wide SIMD architectures.…”

Section: Related Workmentioning

confidence: 99%

A Co-Design Framework with OpenCL Support for Low-Energy Wide SIMD Processor

She

Waeijen

et al. 2014

J Sign Process Syst

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Energy efficiency is one of the most important metrics in embedded processor design. The use of wide SIMD architecture is a promising approach to build energyefficient high performance embedded processors. In this paper, we propose a design framework for a configurable wide SIMD architecture that utilizes an explicit datapath to achieve high energy efficiency. The framework is able to generate processor instances based on architecture specification files. It includes a compiler to efficiently program the proposed architecture with standard programming languages including OpenCL. This compiler can analyze the static memory access patterns in OpenCL kernels, generate efficient mappings, and schedule the code to fully utilize the explicit datapath. Extensive experimental results show that the proposed architecture is efficient and scalable in terms of area, performance, and energy. In a 128-PE SIMD processor, the proposed architecture is able to achieve up to 200 times speed-up and reduce the total energy consumption by 50 % compared to a basic RISC processor.

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Synthesis of Platform Architectures from OpenCL Programs

Cited by 69 publications

References 8 publications

Design of OpenCL-compatible multithreaded hardware accelerators with dynamic support for embedded FPGAs

Design of OpenCL-compatible multithreaded hardware accelerators with dynamic support for embedded FPGAs

Shortening Design Time through Multiplatform Simulations with a Portable OpenCL Golden-model: The LDPC Decoder Case

A Co-Design Framework with OpenCL Support for Low-Energy Wide SIMD Processor

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