Shortening Design Time through Multiplatform Simulations with a Portable OpenCL Golden-model: The LDPC Decoder Case

Abstract

Abstract-Hardware designers and engineers typically need to explore a multi-parametric design space in order to find the best configuration for their designs using simulations that can take weeks to months to complete. For example, designers of special purpose chips need to explore parameters such as the optimal bitwidth and data representation. This is the case for the development of complex algorithms such as Low-Density Parity-Check (LDPC) decoders used in modern communication systems. Currently, high-performance computing offers a wide set of acceleration options, that range from multicore CPUs to graphics processing units (GPUs) and FPGAs. Depending on the simulation requirements, the ideal architecture to use can vary. In this paper we propose a new design flow based on OpenCL, a unified multiplatform programming model, which accelerates LDPC decoding simulations, thereby significantly reducing architectural exploration and design time. OpenCL-based parallel kernels are used without modifications or code tuning on multicore CPUs, GPUs and FPGAs. We use SOpenCL (Silicon to OpenCL), a tool that automatically converts OpenCL kernels to RTL for mapping the simulations into FPGAs. To the best of our knowledge, this is the first time that a single, unmodified OpenCL code is used to target those three different platforms. We show that, depending on the design parameters to be explored in the simulation, on the dimension and phase of the design, the GPU or the FPGA may suit different purposes more conveniently, providing different acceleration factors. For example, although simulations can typically execute more than 3× faster on FPGAs than on GPUs, the overhead of circuit synthesis often outweighs the benefits of FPGA-accelerated execution.

Combining flexibility with low power: Dataflow and wide-pipeline LDPC decoding engines in the Gbit/s era

“…Effectively, whenever a synchronization occurs, the pipeline is flushed. However, as shown in the literature for structured LDPC codes [13], the execution scheduling of BNs and CNs has enough flexibility to be pipelined to some extent. Thus, in order to exploit this flexibility, we manually unrolled the decoding iterations and include both the BN and the CN decoding modes in the same function definition.…”

“…The OpenCL wide-pipeline accelerator has the advantage of rapid prototyping across both CPU and GPU devices [13]. However, it has some scalability issues: 1) the logic utilization of the LDPC wide-pipeline engine saturates for only 2 CUs; 2) although the utilized FPGA board supports a clock frequency of up to 800MHz, the Altera OpenCL compiler sets a maximum pace of 240MHz for a single CU; and 3) in our experiments, the introduction of the second CUs imposed routing constraints that translated into lower clock frequencies, namely the 240MHz that was observed for 1 CU reduced to 157MHz when doubling the number of CUs, thus limiting the potential maximum performance of the decoder.…”

Design of LDPC Decoder Based On FPGA in Digital Image Watermarking Technology

“…In the hardware design of FPGA [4][5][6][7][8], all structure of the LDPC decoder is made up of four modules, which are the information input module, variable node processing units (VNU) module, check node processing units (CNU) module, and the information output module [9][10][11]. Figure.3 is the structure diagram of LDPC decoder in the digital image watermarking system based on the hardware design of FPGA.…”

Enabling development of OpenCL applications on FPGA platforms

“…al [3] proposed a multi-platform framework for accelerating simulations in LDPC (Low Density Parity Check) decoding. The OpenCL programming model was used to target a CPU, GPU and an FPGA without any modifications to the input code and using SOpenCL for mapping OpenCL kernels onto FPGA reconfigurable fabric.…”

“…Different classes of applications employ different targets best suited for the problem at hand. Each of the accelerator technologies possess advantages over the other for variant tasks leading to possibilities of a heterogeneous mix of architectures [1][2][3]. Reconfigurable systems like FPGAs provide promising opportunities for acceleration in many fields due to their inherent flexibility and massive parallel computation capabilities.…”