Synthesis of clock gating logic through factored form matching

Han, Inhak; Shin, Youngsoo

doi:10.1109/icicdt.2012.6232835

Cited by 3 publications

(1 citation statement)

References 9 publications

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“…To the best of our knowledge, no such metrics of EDA effectiveness are available to this day. This approach is close to the aforementioned work in [20] and [21]. Another limitation of synthesis tools is that only statistical information from activity log files is used.…”

Section: Synthesis Considerations and Approachesmentioning

confidence: 63%

Clock gating methodologies and tools: a survey

Pouiklis

2015

Circuit Theory & Apps

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Clock gating (CG) is a widely used design method for reducing the dynamic power consumption in digital circuits. Although it is a mature technique, theoretical work and tools for its application are still evolving and considered a matter of ongoing research, due to its significant effect in the overall power of the designs under study. This paper introduces a detailed review of the spectrum of CG approaches, theoretical and practical, from an architectural and register transfer level to synthesis, place and route, and testing issues. Furthermore, tools availability, limitations, and requirements concerning CG are examined for each design flow step. Conclusively, an evaluation of the presented techniques and literature is provided, estimating their usefulness and identifying areas for future research, exploration, and automation. Figure 3. Basic CG structure. A clock input and a CG function provide the Clk and En signals to the ICG (integrated CG), which generates the gated clock used by the registers. CLOCK GATING METHODOLOGIES AND TOOLS: A SURVEY 801consumption is getting higher on the priorities and risks, during specifications and requirements definition, meaning that power saving exploration needs to be exhaustive. Thus, the research space and tool development for CG applications and optimizations remain as relevant as ever. 816G. POUIKLIS AND G. CH. SIRAKOULIS

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Section: Synthesis Considerations and Approachesmentioning

confidence: 63%

Clock gating methodologies and tools: a survey

Pouiklis

2015

Circuit Theory & Apps

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Generalization of clock gating logic using wide spread adapting technique

Kiruthika¹,

Kavitha²,

Rajan³

2015

2015 2nd International Conference on Electronics and Communication Systems (ICECS)

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The Clock gating reduces dynamic power dissipation in synchronous circuits. The gating function is the process of filtering glitches from a block which is achieved by inserting clock gating cell. Clock gating logic uses strong and weak matching process,they are two kinds of factor form matching.The strong matching seeks for the matches which are externally present in the factored forms and the weak matching identifies matches that are implicit in the logic and they are hard to discover. The clock gating logic can be generalized by using a technique called a Wide Spread Adapting (WSA) clock gating technique which is a modified Boolean function technique. The WSA technique does the matching process by using a WSA algorithm. This WSA technique reduces the clocking signal and the gate pattern. Thus the proposed method achieves reduced clock gating which in turn reduces delay, power, gate count and area.

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Simplifying Clock Gating Logic by Matching Factored Forms

Han

Shin

2014

IEEE Trans. VLSI Syst.

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Synthesis of clock gating logic through factored form matching

Cited by 3 publications

References 9 publications

Clock gating methodologies and tools: a survey

Clock gating methodologies and tools: a survey

Generalization of clock gating logic using wide spread adapting technique

Simplifying Clock Gating Logic by Matching Factored Forms

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