Synthesis Concepts of Signals With High Spectral Purity for the Use in Impulse Radar Systems

Abstract

This paper focuses on the synthesis of ultralow-noise signals for the use in a timebase of impulse radar systems. These systems are used in manifold applications and their accuracy is strongly dependent on the spectral purity of the timebase. Current systems use either phase-locked loops (PLLs) or direct digital synthesizers (DDSs). These PLLs comprise an excessive amount of components and recent DDSs still have a low spuriousfree dynamic range (SFDR). Therefore, this paper presents two new approaches for the direct synthesis. They are based on frequency dividers with both short division factor sequences and noise-shaping techniques. Ideas for spur avoidance and noise reduction are described to improve the noise behavior in terms of SFDR and phase noise. The presented approaches have been realized in hardware and measurement results are depicted. For the system using frequency dividers with short division factor sequences, the best results are a SFDR better than 117 dB at a signal frequency of 10.7 MHz. The phase noise level is below −140 dBc/Hz at offset frequencies greater than 1 kHz. Regarding the frequency dividers with noise-shaping techniques, no discrete spurious are visible. The phase noise level at offset frequencies greater than 7 kHz is below −150 dBc/Hz. These results are comparable with state-of-the-art PLL concepts and thus confirm the approaches.Index Terms-All-digital frequency synthesis, direct frequency synthesis, frequency divider, ground penetrating radar, impulse radar (GPR), phase noise, spurious-free dynamic range (SFDR), time-domain reflectometry (TDR), timebase.

A high resolution DDFS design on VHDL using bipartite table method

“…1. In DDFS designs, many improvements are revealed to achieve better spectral performance [8], lower power dissipation [9], [10], higher frequency resolution [11] and smaller required area [12]- [14]. This paper presents a high resolution, LUT based DDFS design on VHDL.…”