Synthesis and placement flow for gain-based programmable regular fabrics

Hu, Bo; Jiang, Hailin; Liu, Qinghua; Marek-Sadowska, Malgorzata

doi:10.1145/640038.640041

Cited by 6 publications

(9 citation statements)

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“…We use a simplified approach to handle this deviation: when the number of VCCs in the combinational block from equation (5) exceeds N crit , we substitute this number with N crit into equation (5). Experimental curves show that N crit is between 150 to 200 for various circuits, and we simplify it by taking N crit = 175 for all experimental circuits.…”

Section: Estimating the Statistics Of Buffer Distributionmentioning

confidence: 99%

“…Design with structured ASICs involves many fewer masks than for cell-based ASICs. One paradigm that is used involves viaconfigurability, where the building blocks and interconnect skeletons are prefabricated and are then connected with appropriate via connections by programming only a small number of masks [2][3][4][5][6]. A standard building block is composed of combinational logic and memory elements (such as flip-flops) and has enough flexibility that it can be programmed to various functions through via configurations.…”

Section: Introductionmentioning

confidence: 99%

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Buffering global interconnects in structured ASIC design

Zhang

Sapatnekar

2008

Integration

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Structured ASICs present an attractive alternative to reducing design costs and turnaround times in nanometer designs. As with conventional ASICs, such designs require global wires to be buffered. However, via-programmable designs must prefabricate and preplace buffers in the layout. This paper proposes a novel and accurate statistical estimation technique for distributing prefabricated buffers through a layout. It employs Rent's rule to estimate the buffer distribution required for the layout, so that an appropriate structured ASIC may be selected for the design. Experimental results show that the buffer distribution estimation is accurate and economic, and that a uniform buffer distribution can maintain a high degree of regularity in design and shows a good timing performance, comparable with nonuniform buffer distribution.

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Section: Estimating the Statistics Of Buffer Distributionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Buffering global interconnects in structured ASIC design

Zhang

Sapatnekar

2008

Integration

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“…To reduce this area penalty, FPGA vendors use a high number of metal layers, can find studies which focus on Cell-based MPGA synthesis [36] or LUT-based MPGAs architecture exploration [61].…”

Section: Overview Of Existing Solutionsmentioning

confidence: 99%

Automated Conversion From Lut-Based FPGAs to LUT-Based MPGAs

Veredas

Pfleiderer

2006

2006 International Conference on Field Programmable Logic and Applications

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Field-programmable gate-arrays (FPGAs) are used for application-specific standard product (ASIC) prototyping or small volume products. In medium to large volume products, the prototyping design or the small volume product is converted to another integrated circuit (IC) structure such as maskprogrammable gate arrays (MPGAs). MPGAs are of growing importance because of the increase of design cost, and turnaround times in ultra-deep submicron technologies which mostly impact ASICs. Several design methodologies have been proposed in recent years for converting an evaluated FPGA prototype-design into an MPGA. The MPGA design uses potentially less area, delay, and dynamic power consumption than the FPGA design.In a conversion from an FPGA design, the engineer looks for a simple flow to minimize time-to-market. It is well known that the most time consuming process in an IC design is verification. Formal verification checks the functionality of the designed circuit. Physical verification checks the timing (and in same cases the power consumption) of the designed circuit. Formal verification is simplified if the same gate-level netlist of the FPGA is used in the conversion. Simplification of physical verification is possible by exploiting the regularity in the IC layout.In this thesis, two new Look-Up Table-

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“…Therefore, structured ASIC design has the advantage of cost-performance efficiency over FPGA and standard cell design, making it an attractive design style option for modern ASIC design projects. Many research teams have recently targeted structured ASIC generic logic block designs and synthesis methodologies as a result [Ran and Marek-Sadowska 2006a;Patel et al 2003;Hu et al 2003;Jayakumar and Khatri 2004;Gulati et al 2007;Li et al 2008].…”

Section: Introductionmentioning

confidence: 99%

Routability optimization for crossbar-switch structured ASIC design

Tsai

Hsu

et al. 2013

ACM Trans. Des. Autom. Electron. Syst.

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In the routing architecture of a structured application-specific integrated circuit (ASIC), the crossbar is one of the most area-efficient switch blocks. Nevertheless, a dangling wire occurs when there is a routing bend in a crossbar switch. Dangling wires incur longer wire lengths as well as a higher interconnection capacitance. In this article, we tackle dangling wire issues for structured ASIC routability optimization. We first propose a compact graph model for crossbar-switch routing. With our graph model, switch connectivity relations can be removed to keep the 2D structured ASIC routing graph efficient and to speed up the runtime of our routing algorithm. Furthermore, we propose a heuristic dangling-wire-avoidance routing framework containing deferred pin assignment, Steiner point reassignment, and anchor pair insertion in order to minimize dangling wires and channel width. Finally, in order to take routing bends and channel width into account simultaneously, we propose concurrent and sequential integer linear programming (ILP) formulations and ILP variable/constraint degeneration techniques. The experimental results demonstrate that our proposed heuristic routing framework reduces dangling wires by 19%, channel width by 38%, and wire length by 13% to VPR using the crossbar switch (VPR-C). In addition, our sequential ILP router reduces dangling wires by 38%, channel width by 40%, and wire length by 15% compared to VPR-C. Thus, the runtime efficiency of our sequential ILP router is attractive for crossbar-switch structured ASIC routing.

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Synthesis and placement flow for gain-based programmable regular fabrics

Cited by 6 publications

References 0 publications

Buffering global interconnects in structured ASIC design

Buffering global interconnects in structured ASIC design

Automated Conversion From Lut-Based FPGAs to LUT-Based MPGAs

Routability optimization for crossbar-switch structured ASIC design

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