Automated Conversion From Lut-Based FPGAs to LUT-Based MPGAs

Abstract

Field-programmable gate-arrays (FPGAs) are used for application-specific standard product (ASIC) prototyping or small volume products. In medium to large volume products, the prototyping design or the small volume product is converted to another integrated circuit (IC) structure such as maskprogrammable gate arrays (MPGAs). MPGAs are of growing importance because of the increase of design cost, and turnaround times in ultra-deep submicron technologies which mostly impact ASICs. Several design methodologies have been proposed in recent years for converting an evaluated FPGA prototype-design into an MPGA. The MPGA design uses potentially less area, delay, and dynamic power consumption than the FPGA design.In a conversion from an FPGA design, the engineer looks for a simple flow to minimize time-to-market. It is well known that the most time consuming process in an IC design is verification. Formal verification checks the functionality of the designed circuit. Physical verification checks the timing (and in same cases the power consumption) of the designed circuit. Formal verification is simplified if the same gate-level netlist of the FPGA is used in the conversion. Simplification of physical verification is possible by exploiting the regularity in the IC layout.In this thesis, two new Look-Up Table-