Synchronous techniques for timing recovery in BISDN

Lau, R.C.; Fleischer, P.E.

doi:10.1109/26.380232

Cited by 36 publications

(20 citation statements)

References 8 publications

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“…This is commonly done using a phase-locked loop (PLL) that slaves the receiver clock to a transmitter clock (Figure 1). The PLL is able to process transmitted clock samples encoded within the data stream [5,6], or process data arrival patterns [7][8][9][10] to generate timing signal for the receiver. The purpose of the PLL is to estimate and compensate for the frequency drift occurring between the oscillators of the transmitter clock and the receiver clock.…”

Section: Clock Recovery Based On Packet Inter-arrival Time Averagingmentioning

confidence: 99%

Analysis of a clock‐recovery technique for circuit emulation services over packet networks

Aweya

Montuno

Ouellette

et al. 2007

Int J Communication

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SUMMARYOne important requirement of circuit emulation services (CES) over packet networks is clock synchronization and timing distribution among the nodes. CES depends on reliable and high-quality timing for operations. In the time division multiplexing (TDM) world, whether plesiochronous digital hierarchy (PDH), synchronous digital hierarchy (SDH) or synchronous optical network (SONET) based, timing and synchronization is inherent in the design of the network. However, when timing critical services such PDH and SDH/SONET are carried over packet network (e.g. IP, Ethernet, etc.), the timing element is lost and has to be carried across the packet network by other means. A well-known and widely implemented technique for clock recovery in CES is one that is based on packet inter-arrival time (sometimes called time difference of arrival) averaging. The technique is very simple to implement but provides good performance only when packet losses and packet delay variation (PDV) are very low and well controlled. This technique has been extensively analysed through simulations but has not been fully characterized analytically with correlated traffic in the literature. In this paper, we provide a full analytical examination of this well-known clock recovery technique. We analyse the effects of correlation of the delay variation in the traffic stream on the quality of the clock recovered by a receiver. We prove analytically that, for a general input process, high correlation of the delay variation produces a large variance of the recovered clock.

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Section: Clock Recovery Based On Packet Inter-arrival Time Averagingmentioning

confidence: 99%

Analysis of a clock‐recovery technique for circuit emulation services over packet networks

Aweya

Montuno

Ouellette

et al. 2007

Int J Communication

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“…An example of such an approach is used in the transfer of timing information for CBR transmission over asynchronous transfer mode (ATM) Adaptation Layer 1 (AAL1) by the synchronous residual time stamp (SRTS) method [1]. It has been shown that such timing-transfer techniques are similar to rate adaptation by bit stuffing [2] and pointer adjustment [3], and the jitter generated is similar to waiting-time jitter [1], [3], [4]. Waiting-time jitter is deterministic jitter, and can accumulate significantly from repeater to repeater [5], whereas jitter accumulation in synchronous networks is prevented by limiting the number of allowed pointer adjustments [3].…”

Section: Introductionmentioning

confidence: 99%

“…As the exact number of reference clock cycles in is usually not an integer, the result is a quantized representation of the service clock with interpulse intervals , where takes on one of two possible values: or , such that the long-term average period is [6]. The resulting jitter on the quantized clock, , is also the jitter present on the recovered timing signal at the destination, and is given by (1) The spectrum of this jitter can be expressed as (2) Paper approved by C. In previous analyses, it has been assumed that the clocks are ideal, whereas in real systems, the assumption of ideal clocks does not hold. In [2] and [7], consideration was given to the effect of jitter on the service clock.…”

Section: Introductionmentioning

confidence: 99%

Modeling the Effect of Nonideal Reference Clocks on the Jitter Generated in Timing Transfer

Walker

Cantoni²

2007

IEEE Trans. Commun.

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“…Equation (3) has been studied in the context of communication systems [17] and the solution is given by:…”

Section: Coherent Clocksmentioning

confidence: 99%

MTBF Estimation in Coherent Clock Domains

Beer

Ginosar

Dobkin

et al. 2013

2013 IEEE 19th International Symposium on Asynchronous Circuits and Systems

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Abstract-Special synchronizers exist for special clock relations such as mesochronous, multi-synchronous and ratiochronous clocks, while variants of N-flip-flop synchronizers are employed when the communicating clocks are asynchronous. N-flip-flop synchronizers are also used in all special cases, at the cost of longer latency than when using specialized synchronizers. The reliability of N-flip-flop synchronizers is expressed by the standard MTBF formula. This paper describes cases of coherent clocks that suffer of a higher failure rate than predicted by the MTBF formula; that formula assumes uniform distribution of data edges across the sampling clock cycle, but coherent clocking leads to drastically different situations. Coherent clocks are defined as derived from a common source, and phase distributions are discussed. The effect of jitter is analyzed, and a new MTBF expression is developed. An optimal condition for maximizing MTBF and a circuit that can adaptively achieve that optimum are described. We show a case study of metastability failure in a real 40nm circuit and describe guidelines used to increase its MTBF based on the rules derived in the paper.

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Synchronous techniques for timing recovery in BISDN

Cited by 36 publications

References 8 publications

Analysis of a clock‐recovery technique for circuit emulation services over packet networks

Analysis of a clock‐recovery technique for circuit emulation services over packet networks

Modeling the Effect of Nonideal Reference Clocks on the Jitter Generated in Timing Transfer

MTBF Estimation in Coherent Clock Domains

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