Synchronous FPGA-Based High-Resolution Implementations of Digital Pulse-Width Modulators

Navarro, D.; Lucía, Óscar; Barragán, L.A.; Artigas, J.I.; Urriza, I.; Jiménez, O.

doi:10.1109/tpel.2011.2173702

Cited by 70 publications

(31 citation statements)

References 36 publications

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“…The IODELAYE tap resolution is given by ( ) The RS latch in the advanced DPWM is easy to impact on timing and always affected by the temperature, so the function is not stable [1]. As a result, this new DPWM control circuit uses the OR gate to realize the function of RS latch, making the DPWM more stable.…”

Section: The Principle Of Dpwmmentioning

confidence: 99%

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An Improved High-Resolution DPWM Control Circuit Based on FPGA

Hu¹,

Li²,

Yuan³

2017

dtetr

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Abstract. Digital pulse width modulation (DPWM) has advantages of strong anti-interference ability, high efficiency and good flexibility, therefore it has been widely used in switching power supply, communications, power control and transform and other fields. This paper proposed a high resolution DPWM control circuit based on field programmable gate array (FPGA), which solved the problem of low resolution and instability of the traditional DPWM control circuit. The principle of the proposed circuit is presented in this paper, and the circuit has been successfully implemented on the Xilinx Artix-7 FPGA development board. The experiment shows that, when the frequency of the circuit is 50 MHz, the resolution of DPWM can reach 78ps, and the proposed DPWM control circuit has wide application prospects.

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Section: The Principle Of Dpwmmentioning

confidence: 99%

“…In recent years, DPWM has been widely used in many power converters. The resolution of DPWM is the main factor affecting the accuracy in the output voltage/current control which determines the performance of the power converter [1,2].…”

Section: Introductionmentioning

confidence: 99%

An Improved High-Resolution DPWM Control Circuit Based on FPGA

Hu¹,

Li²,

Yuan³

2017

dtetr

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“…The system can be controlled using a self-adaptive loop and must have an operating frequency slightly greater than the resonant frequency of the tank circuit, which comprises an induction-coil-heated piece in series with a resonant capacitor. The high-frequency induction heating inductor current can be controlled by adjusting either the output current or output voltage of the inverter, and the high-frequency control loop is sufficient to control these two output parameters [11][12][13][14][15][16].…”

Section: Introductionmentioning

confidence: 99%

A closed-loop power controller model of series-resonant-inverter-fitted induction heating system

Pal¹,

Roy²,

Datta³

et al. 2016

Archives of Electrical Engineering

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This paper presents a mathematical model of a power controller for a high-frequency induction heating system based on a modified half-bridge series resonant inverter. The output real power is precise over the heating coil, and this real power is processed as a feedback signal that contends a closed-loop topology with a proportional-integral-derivative controller. This technique enables both control of the closed-loop power and determination of the stability of the high-frequency inverter. Unlike the topologies of existing power controllers, the proposed topology enables direct control of the real power of the high-frequency inverter.

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“…Several architectures were developed for DPWM operating in the frequency range from KHz to MHz. These include the Counter Comparator based DPWM, Delay line based DPWM, Hybrid Delay line based DPWM architectures [6] and many soft computing techniques [7] [8], each of it having its own advantage and disadvantage. All these architectures have come with an improvement in area, linearity, speed, minimized delay and minimized power consumption.…”

Section: Introductionmentioning

confidence: 99%

FPGA-Based High-Frequency Digital Pulse Width Modulator Architecture for DC-DC Converters

Radhika¹,

Baskaran²

2016

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Digital pulse width modulator is an integral part in digitally controlled Direct Current to Direct Current (DC-DC) converter utilized in modern portable devices. This paper presents a new Digital Pulse Width Modulator (DPWM) architecture for DC-DC converter using mealy finite state machine with gray code encoding scheme and one hot encoding method to derive the variable duty cycle Pulse Width Modulation (PWM) signal without varying the clock frequency. To verify the proposed DPWM technique, the architecture with control input of six, five and four bits are implemented and the maximum operating frequency along with power consumption results is obtained for different Field Programmable Gate Array (FPGA) devices. The post layout timing results are presented showing that architecture can work with maximum frequency of 326 MHz and derive PWM signal of 3.59 MHz. Experimental results show the implementation of the proposed architecture in low-cost FPGA (Spartan 3A) with on-board oscillator clock frequency of 12 MHz which is multiplied internally by two with Digital Clock Manager (DCM) and derive the PWM signal of 1.5 MHz with a time resolution of 1 ps.

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Synchronous FPGA-Based High-Resolution Implementations of Digital Pulse-Width Modulators

Cited by 70 publications

References 36 publications

An Improved High-Resolution DPWM Control Circuit Based on FPGA

An Improved High-Resolution DPWM Control Circuit Based on FPGA

A closed-loop power controller model of series-resonant-inverter-fitted induction heating system

FPGA-Based High-Frequency Digital Pulse Width Modulator Architecture for DC-DC Converters

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