Synchronizing sequences and symbolic traversal techniques in test generation

Cho, Hyunwoo; Jeong, Seh-Woong; Somenzi, Fabio; Pixley, Carl

doi:10.1007/bf00971937

Cited by 72 publications

(28 citation statements)

References 15 publications

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“…Hachtel et al [36,23] show that aperiodic FSMs with strongly-connected state spaces eventually reach a steady-state distribution. A modulo-d counter is an example of such an FSM.…”

Section: Steady-state and Reachability Analysismentioning

confidence: 99%

Design, Analysis and Test of Logic Circuits Under Uncertainty

Krishnaswamy¹,

Markov²,

Hayes³

2013

Lecture Notes in Electrical Engineering

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“…Hachtel et al [36,23] show that aperiodic FSMs with strongly-connected state spaces eventually reach a steady-state distribution. A modulo-d counter is an example of such an FSM.…”

Section: Steady-state and Reachability Analysismentioning

confidence: 99%

Design, Analysis and Test of Logic Circuits Under Uncertainty

Krishnaswamy¹,

Markov²,

Hayes³

2013

Lecture Notes in Electrical Engineering

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“…The use of ROBDDs for exact simulation in synchronous sequential circuits has been proposed in [19]. Since this approach is limited by the memory requirements of the BDD, the authors of [20] propose a hybrid fault simulation approach which uses exact ROBDD-based symbolic simulation until the ROBDD memory requirement exceeds a given limit.…”

Section: B Fault Simulation With Increased Accuracymentioning

confidence: 99%

SAT-based fault coverage evaluation in the presence of unknown values

Kochte

Wunderlich

2011

2011 Design, Automation &Amp; Test in Europe

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Fault simulation of digital circuits must correctly compute fault coverage to assess test and product quality. In case of unknown values (X-values), fault simulation is pessimistic and underestimates actual fault coverage, resulting in increased test time and data volume, as well as higher overhead for design-for-test. This work proposes a novel algorithm to determine fault coverage with significantly increased accuracy, offering increased fault coverage at no cost, or the reduction of test costs for the targeted coverage. The algorithm is compared to related work and evaluated on benchmark and industrial circuits. Preprint General Copyright NoticeThis article may be used for research, teaching and private study purposes. Any substantial or systematic reproduction, re-distribution, re-selling, loan or sub-licensing, systematic supply or distribution in any form to anyone is expressly forbidden. This is the author's "personal copy" of the final, accepted version of the paper published by IEEE. Abstract-Fault simulation of digital circuits must correctly compute fault coverage to assess test and product quality. In case of unknown values (X-values), fault simulation is pessimistic and underestimates actual fault coverage, resulting in increased test time and data volume, as well as higher overhead for designfor-test. This work proposes a novel algorithm to determine fault coverage with significantly increased accuracy, offering increased fault coverage at no cost, or the reduction of test costs for the targeted coverage. The algorithm is compared to related work and evaluated on benchmark and industrial circuits.

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“…Previously, homing, synchronizing, and distinguishing sequences have been used to aid the test generator in improving the fault coverage [1,2,3,4,5]. In [1,2,4], symbolic and statetable-based techniques were used to derive these sequences in the fault-free machine.…”

Section: Introductionmentioning

confidence: 99%

“…In [1,2,4], symbolic and statetable-based techniques were used to derive these sequences in the fault-free machine. Specically, i n [ 1 ] , c u b e i n tersections of ON/OFF-set representations were used to derive distinguishing sequences.…”

Section: Introductionmentioning

confidence: 99%

“…Specically, i n [ 1 ] , c u b e i n tersections of ON/OFF-set representations were used to derive distinguishing sequences. Binary decision diagrams (BDD's) and implicit state enumeration were used in [2] to derive synchronizing sequences. In the work by P ark et al, [4], functional information was used to pre-generate sequences which simplied propagation of fault eects from the ip-ops to the primary outputs (PO's), and state justication was done by using BDD's.…”

Section: Introductionmentioning

confidence: 99%

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Sequential circuit test generation using dynamic state traversal

Hsiao¹

Proceedings European Design and Test Conference. ED &Amp; TC 97

121

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A new method for state justication is proposed for sequential circuit test generation. The linear list of states dynamically obtained during the derivation of test vectors is used to guide the search during state justication. State-transfer sequences may already be known that drive the circuit from the current state to the target state. Otherwise, genetic engineering of existing state-transfer sequences is required. In both cases, genetic-algorithm-based techniques are used to generate valid state justication sequences for the circuit in the presence of the target fault. This approach achieves extremely high fault coverages and thus outperforms previous deterministic and simulation-based techniques.

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Synchronizing sequences and symbolic traversal techniques in test generation

Cited by 72 publications

References 15 publications

Design, Analysis and Test of Logic Circuits Under Uncertainty

Design, Analysis and Test of Logic Circuits Under Uncertainty

SAT-based fault coverage evaluation in the presence of unknown values

Sequential circuit test generation using dynamic state traversal

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