Synchronizing Code Execution on Ultra-Low-Power Embedded Multi-Channel Signal Analysis Platforms

Abstract

Abstract-Embedded biosignal analysis involves a considerable amount of parallel computations, which can be exploited by employing low-voltage and ultra-low-power (ULP) parallel computing architectures. By allowing data and instruction broadcasting, single instruction multiple data (SIMD) processing paradigm enables considerable power savings and application speedup, in turn allowing for a lower voltage supply for a given workload. The state-of-the-art multi-core architectures for biosignal analysis however lack a bare, yet smart, synchronization technique among the cores, allowing lockstep execution of algorithm parts that can be performed using the SIMD, even in the presence of data-dependent execution flows. In this paper, we propose a lightweight synchronization technique to enhance an ULP multicore processor, resulting in improved energy efficiency through lockstep SIMD execution. Our results show that the proposed improvements accomplish tangible power savings, up to 64% for an 8-core system operating at a workload of 89 MOps/s while exploiting voltage scaling.

Hardware/software approach for code synchronization in low-power multi-core sensor nodes

“…In this scenario, substantial energy gains can be achieved when multiple cores execute the same phases of an application (e.g., conditioning in Figure 1) on multiple acquired inputs, as demonstrated by the authors of [11] and [8]. However, these synchronization approaches do not provide the necessary flexibility to perform parallel processing of streams on multiple cores, while also supporting producer-consumer relationships among cores.…”

“…: they are at the same point of the program flow, so that a single instruction is fetched and delivered in parallel. Indeed, a mechanism to recover lockstep execution across data-dependent branches was proposed in [8]. Nonetheless, the introduced paradigm has the limiting assumption that each core executes the same program flow on a different data stream, which restricts the range of applications that can be targeted.…”

“…As aforementioned, the synchronization instructions can also enforce lock-step execution among cores across datadependent branches (Figure 3-b), by employing the methodology described by the authors of [8]. In this case, before entering a branch, cores execute a SINC instruction.…”

“…In fact, in addition to filtering inputs, it also aggregates them and analyses the resulting combined streams to automatically detect the ECG fiducial points. Consequently, as opposed to 3L-MF, it cannot be mapped using the technique described in [8]. The application is mapped onto five cores, of which three perform filtering in parallel and two are employed to combine the signals and identify the fiducial points, respectively.…”

“…Aggressive VFS [6] can nonetheless degrade run-time performance below the requirements of the target application, so that parallel computations have to be performed to achieve the required throughput [7]. Low-power multi-core WBSNs, thus, appear as promising candidates to improve energy efficiency, exploiting the benefits of single-instructions-multiple-data (SIMD) architectures when executing code synchronously [8]. Devising synchronization techniques for multi-core platforms is often domain-specific, as trade-offs must be considered between flexibility and efficiency of implementations.…”