Synaptic Devices Based on 3-D AND Flash Memory Architecture for Neuromorphic Computing

Noh, Yoohyun; Seo, Young-Tak; Park, Byunggook; Lee, Jong-Ho

doi:10.1109/imw.2019.8739698

Cited by 18 publications

(12 citation statements)

References 7 publications

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“…In addition, the AND‐type synaptic device can achieve ultra‐high density based on the use of 3D VNAND fabrication techniques. [ 188 ]…”

Section: Synaptic Devices For Neuromorphic Computingmentioning

confidence: 99%

“…Studies were conducted to utilize 3D AND-type flash memory as a synaptic device. [188,189] Although 3D AND flash devices did not exhibit the required properties for a synaptic device such as multilevel conductance, gradual conductance change, and high on/off ratio, several distinct merits were observed. The 3D AND flash-based synaptic devices allow for faster read operation because all devices are connected in parallel to perform read operations simultaneously.…”

Section: D Flash Memory As Synaptic Devicementioning

confidence: 99%

See 1 more Smart Citation

Recent Advances in Synaptic Nonvolatile Memory Devices and Compensating Architectural and Algorithmic Methods Toward Fully Integrated Neuromorphic Chips

Byun

Choi

Kwon

et al. 2022

Adv Materials Technologies

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Nonvolatile memory (NVM)‐based neuromorphic computing has been attracting considerable attention from academia and the industry. Although it is not completely successful yet, remarkable achievements have been reported pertaining to synaptic devices that can leverage NVM capable of storing multiple states. The analog synaptic devices performing computation similar to biological nerve systems are crucial in energy‐efficient analog neuromorphic computing systems. To use NVM as an analog synaptic device, researchers focus on improving device characteristics. Among various characteristics, the most challenging one is linearity and symmetry of synaptic weight update that is required for on‐chip training. In this regard, this review paper discusses recent synaptic device improvements focusing on novel schemes tailored for each NVM device to improve the linearity and symmetry. In addition to device‐level studies, recent research achievements are reviewed expanded up to chip‐level studies because in realizing neuromorphic hardware systems beyond a single synaptic device, several considerations and requirements are needed to confirm for high‐level design, and accordingly, cooptimize among synaptic devices, synapse arrays, electrical circuits, neural networks, algorithms, and implementation. Also, this review paper introduces various circuit and algorithmic approaches to compensate for the non‐ideality of the analog synaptic device.

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“…In addition, the AND‐type synaptic device can achieve ultra‐high density based on the use of 3D VNAND fabrication techniques. [ 188 ]…”

Section: Synaptic Devices For Neuromorphic Computingmentioning

confidence: 99%

Section: D Flash Memory As Synaptic Devicementioning

confidence: 99%

Recent Advances in Synaptic Nonvolatile Memory Devices and Compensating Architectural and Algorithmic Methods Toward Fully Integrated Neuromorphic Chips

Byun

Choi

Kwon

et al. 2022

Adv Materials Technologies

View full text Add to dashboard Cite

show abstract

“…[3][4][5][6][7] Owing to such remarkable technological advances, flash memory has been extensively used as primary storage, from memory cards to data centers, and is also a viable choice as a primitive cell for in-memory computing architecture. [8][9][10][11] The concept of in-memory computing can dramatically reduce data-transferring energy between memory and computing units by performing most computations in the memory device array. Therefore, in-memory computing architecture requires core memory devices exhibiting (i) fast operating speed for energy efficiency, (ii) uniform and stable memory characteristics for accurate computing, and (iii) capability of high-density integration for big data processing.…”

Section: Introductionmentioning

confidence: 99%

“…Moreover, by storing multiple bits in three‐dimensionally integrated memory cells, the limitation of in‐plane scaling has been overcome, along with reduction in cost per bit 3–7 . Owing to such remarkable technological advances, flash memory has been extensively used as primary storage, from memory cards to data centers, and is also a viable choice as a primitive cell for in‐memory computing architecture 8–11 . The concept of in‐memory computing can dramatically reduce data‐transferring energy between memory and computing units by performing most computations in the memory device array.…”

Section: Introductionmentioning

confidence: 99%

Ferro‐floating memory: Dual‐mode ferroelectric floating memory and its application to in‐memory computing

Park

Lee

et al. 2022

InfoMat

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Various core memory devices have been proposed for utilization in future in‐memory computing technology featuring high energy efficiency. Flash memory is considered as a viable choice owing to its high integration density, stability, and reliability, which has been verified by commercialized products. However, its high operating voltage and slow operation speed issues caused by the tunneling mechanism make its adoption in in‐memory computing applications difficult. In this paper, we introduce a dual‐mode memory device named “ferro‐floating memory”, fabricated using van der Waals (vdW) materials (h‐BN, MoS2, and α‐In2Se3). The vdW material, α‐In2Se3, acts as a polarization control layer for the ferroelectric memory operation and charge storage layer for the conventional flash memory operation. Compared to the tunneling‐based memory operation, the ferro‐floating memory operates 1.9 and 3.3 times faster at 6.7 and 5.8 times lower operating voltages for programming and erasing operations, respectively. The dual‐mode operation improves the linearity of conductance change by 5 times and the dynamic range by 48% through achieving conductance variation regions. Furthermore, we assess the effects of the variation in device operating voltage on neural networks and suggest a memory array operating scheme for maximizing the networks' performance through various training/inference simulations.

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“…Another synaptic device candidate is flash memory, which is quite mature and has the advantage of stable operation.in particular, NOR/AND-type flash memory has been studied in an effort to implement a synaptic array [ 11 , 12 , 13 , 14 , 15 , 16 , 17 , 18 ]. However, the cell size in this case exceeds that of memristors, and there are challenges when attempting to scale a large number of synapse arrays.…”

Section: Introductionmentioning

confidence: 99%

3D AND-Type Stacked Array for Neuromorphic Systems

et al. 2020

Self Cite

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NOR/AND flash memory was studied in neuromorphic systems to perform vector-by-matrix multiplication (VMM) by summing the current. Because the size of NOR/AND cells exceeds those of other memristor synaptic devices, we proposed a 3D AND-type stacked array to reduce the cell size. Through a tilted implantation method, the conformal sources and drains of each cell could be formed, with confirmation by a technology computer aided design (TCAD) simulation. In addition, the cell-to-cell variation due to the etch slope could be eliminated by controlling the deposition thickness of the cells. The suggested array can be beneficial in simple program/inhibit schemes given its use of Fowler–Nordheim (FN) tunneling because the drain lines and source lines are parallel. Therefore, the conductance of each synaptic device can be updated at low power level.

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Synaptic Devices Based on 3-D AND Flash Memory Architecture for Neuromorphic Computing

Cited by 18 publications

References 7 publications

Recent Advances in Synaptic Nonvolatile Memory Devices and Compensating Architectural and Algorithmic Methods Toward Fully Integrated Neuromorphic Chips

Recent Advances in Synaptic Nonvolatile Memory Devices and Compensating Architectural and Algorithmic Methods Toward Fully Integrated Neuromorphic Chips

Ferro‐floating memory: Dual‐mode ferroelectric floating memory and its application to in‐memory computing

3D AND-Type Stacked Array for Neuromorphic Systems

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