Symmetry within the sequence-pair representation in the context of placement for analog design

Balasa, Florin; Lampaert, Koen

doi:10.1109/43.851988

Cited by 97 publications

(154 citation statements)

References 23 publications

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“…In this work, we focus on sequence-pair based floorplanning as sequence-pair is one of the most known floorplan representations and has been successfully applied in handling symmetry constraints [2,3]. In section 3.5, we will briefly discuss the regularity constraint in other floorplan representations.…”

Section: Regularity In Relative Ordermentioning

confidence: 99%

“…There is a large body of analog circuit layout works focusing on the symmetry constraints. In [2], a symmetry-constrained analog block placement method is proposed. This work is based on a typical floorplanning approach -simulated annealing with sequence-pair representation.…”

Section: Previous Work With Symmetry Constraintsmentioning

confidence: 99%

“…The regularity constraint to an array group of m blocks implies that these blocks must be placed in a p×q array, where p×q is a factorization of m. The q blocks in one row must appear as a common subsequence [15] in the sequence-pair. For example, the floorplan of Figure 3 can be specified by sequence-pair (<0 1 2 3 4 5>, <2 1 0 5 4 3>), which contains 3 common subsequences (0, 3), (1,4) and (2,5) for the 3 rows. This concept of common subsequence is similar to H-alignment in [16].…”

Section: Regularity In Relative Ordermentioning

confidence: 99%

See 2 more Smart Citations

Regularity-constrained floorplanning for multi-core processors

Chen¹,

Hu²,

Xu³

2014

Integration

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Section: Regularity In Relative Ordermentioning

confidence: 99%

Section: Previous Work With Symmetry Constraintsmentioning

confidence: 99%

Section: Regularity In Relative Ordermentioning

confidence: 99%

See 1 more Smart Citation

Regularity-constrained floorplanning for multi-core processors

Chen¹,

Hu²,

Xu³

2014

Integration

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“…Lin et al [15] also presented the symmetric-feasible conditions for the TCG-S representation. Three more recent works [16]- [18] further took advantage of the symmetric-feasible condition in SPs [8]. Koda et al [16] proposed a linear-programming-based method, and Tam et al [17] introduced a dummy node and additional constraint edges for each symmetry group after obtaining a symmetric-feasible SP.…”

Section: A Previous Workmentioning

confidence: 99%

“…Balasa et al derived the symmetric-feasible conditions for several popular floorplan representations including sequence pairs (SPs) [8], O-tree [9], and binary trees [10]. To explore the solution space in the symmetric-feasible binary trees, they augmented the B * -tree [11] using various data structures, including segment trees [3], [12], red-black trees [13], and deterministic skip lists [14].…”

Section: A Previous Workmentioning

confidence: 99%

Analog Placement Based on Symmetry-Island Formulation

Lin

Chang

Lin³

2009

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-To reduce the effect of parasitic mismatches and circuit sensitivity to thermal gradients or process variations for analog circuits, some pairs of modules need to be placed symmetrically with respect to a common axis, and the symmetric modules are preferred to be placed at closest proximity for better electrical properties. Most previous works handle the problem with symmetry constraints by imposing symmetric-feasible conditions in floorplan representations and using cost functions to minimize the distance between symmetric modules. Such approaches are inefficient due to the large search space and cannot guarantee the closest proximity of symmetry modules. In this paper, we present the first linear-time-packing algorithm for the placement with symmetry constraints using the topological floorplan representations. We first introduce the concept of a symmetry island which is formed by modules of the same symmetry group in a single connected placement. Based on this concept and the B * -tree representation, we propose automatically symmetric-feasible (ASF) B * -trees to directly model the placement of a symmetry island. We then present hierarchical B * -trees (HB * -trees) which can simultaneously optimize the placement with both symmetry islands and nonsymmetric modules. Unlike the previous works, our approach can place the symmetry modules in a symmetry group in close proximity and significantly reduce the search space based on the symmetry-island formulation. In particular, the packing time for an ASF-B * -tree or an HB * -tree is the same as that for a plain B * -tree (only linear) and much faster than previous works. Experimental results show that our approach achieves the best-published quality and runtime efficiency for analog placement.

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Symmetry‐aware placement algorithm using transitive closure graph representation for analog integrated circuits

Zhang

Jiang

et al. 2008

Circuit Theory & Apps

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SUMMARYRecently several topological representations have been explored as alternatives to the conventional absolute-coordinate representation for integrated circuit layout automation. Those topological representations, however, lack one or more aspects in capturing the solution space subject to symmetry constraints, which are abundant in analog layouts.In this paper, we explore the use of transitive closure graphs (TCGs) to represent analog placements, i.e. placements with symmetry constraints. We define a set of conditions so that a TCG satisfying these conditions, referred to as a symmetric-feasible TCG, will correspond to a valid symmetric placement and vice versa. We then present an O(n 2 ) algorithm, where n is the number of cells to be placed, to build a symmetric placement from a symmetric-feasible TCG, a problem known as packing.We further describe a set of random perturbation operations on existing symmetric-feasible TCGs to generate new symmetric-feasible TCGs with time complexity of O(n). This allows our TCG-based symmetry-aware analog placer to search only the symmetric-feasible TCG solution space, leading to a substantial reduction of the search space and solution time. Experimental results on several analog circuits have confirmed the superiority of the TCG representation to the conventional absolute-coordinate representation as well as several other topological representations in analog layout design.

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Symmetry within the sequence-pair representation in the context of placement for analog design

Cited by 97 publications

References 23 publications

Regularity-constrained floorplanning for multi-core processors

Regularity-constrained floorplanning for multi-core processors

Analog Placement Based on Symmetry-Island Formulation

Symmetry‐aware placement algorithm using transitive closure graph representation for analog integrated circuits

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