Symmetry‐aware placement algorithm using transitive closure graph representation for analog integrated circuits

From the industrial perspective, floorplanning is a crucial step in the VLSI physical design process as its efficiency determines the quality and the time-to-market of the product. A new perturbation method, called Cull-and-Aggregate Bottom-up Floorplanner (CABF), which consists of culling and aggregating stages, is developed to perform variable-order automated floorplanning for VLSI. CABF will generate VLSI floorplan layout by calculating the modules' dimensions' differences (hard module floorplanning problems) and the modules' areas' differences (soft module floorplanning problems). Through mathematical derivation, the hard modules floorplanning area minimization cost function (two-dimensional) during culling stage is proven that a dimensional reduction can be carried out to be the difference-based cost function (one-dimensional) which simplifies the computation. During the culling stage, CABF employs linear ordering method to select and determine the order of modules where this linear runtime complexity property allows CABF to cull the modules faster. The aggregating stage of CABF will reduce the subsequent search space of this floorplanner, and the variable order aggregation enables CABF to search for the best near-optimal solution. Based on Gigascale Systems Research Center and Microelectronics Center of North Carolina circuit benchmarks, CABF gives better optimal solutions and faster runtimes for floorplanning problems involving 9 to 600 modules. This has established that CABF is performing well in respect of reliability and scalability. Besides, CABF shows its potential to be implemented in VLSI physical design as the runtime of CABF is faster with a near-optimal outcome as compared to the other existing algorithms.

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Cost reduction in bottom‐up hierarchical‐based VLSI floorplanning designs

Hoo

Kanesan

Ramiah

2013

“…The objective is to minimize the area and wire length with the fixed‐outline constraint. After partitioning , the relative location of the different modules needs to be decided before the placement stage (i.e., placing the cells in the relative location), with the objective of minimizing the total area occupied by the components. The floorplanning problem has been proved to be Non‐deterministic Polynomial‐time (NP) hard .…”

Section: Introductionmentioning

confidence: 99%

A multiobjective optimization tool for Very Large Scale Integrated nonslicing floorplanning

Anand

Saravanasankar

Subbaraj

2012

Floorplanning is a vital phase in the design process of Very Large Scale Integrated (VLSI) circuit physical design process. The main objective of floorplanning is to minimize the area and wire length with the fixedoutline constraints. Most of the tools developed so for are using weighted some approach. Hence, these tools suffer from weights assignment and undesirable bias toward particular objective. A tailor-made multiobjective optimization tool could overcome this issue.In this article, we propose a new multiobjective optimization technique named self adaptive B*tree coded Archived Multiobjective Simulated Annealing Algorithm (AMOSA) and implemented to solve the VLSI nonslicing floorplanning problem. The proposed model provides choices from among different trade-off solutions. The self adaptive B*tree coded AMOSA combines the novel cooling schedule, B*tree encoding, improved neighborhood search procedure, self adaptive local search, and the AMOSA. In B*tree coded AMOSA, the solution is represented using a B*tree. This representation causes a reduction in time and space complexity of AMOSA. The B*tree coded AMOSA is further improved with a novel cooling schedule, a self adaptive local search mechanism, and an improved neighborhood search procedure, resulting in further reduction of computational time and improvement in exploration capability. The FastSA, B*tree coded AMOSA, and the self adaptive B*tree coded AMOSA are tested with Microelectronics Center of North Carolina (MCNC) benchmarks. The results are compared and validated. The proposed method shows 59.8% improvement in the computational time for ami49 without changing the system quality.

“…

Multi-voltage techniques are being developed to improve power savings by providing lower supply voltages for noncritical blocks under the performance constraint. With exploding design complexity, it is necessary to consider voltage drop issues in the early design cycle [14][15][16][17]. For voltage drop optimization, both block and power pad positions are important factors that need to be considered.

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mentioning

confidence: 99%

“…However, those techniques are implemented only when the floorplan or placement is ready. With exploding design complexity, it is necessary to consider voltage drop issues in the early design cycle [14][15][16][17]. Once the voltage drops aware floorplan is obtained, the detailed P/G network design can be performed in the subsequent placement and routing stages that consider Steiner tree construction and electromigration issues [18,19].It is reported that 5% of voltage decrease may cause the circuit performance slowdown up to 15% or more [20].…”

mentioning

confidence: 99%

Efficient power pad assignment for multi‐voltage SoC and its application in floorplanning

Chu

Xia

Wang

et al. 2015

Multi-voltage techniques are being developed to improve power savings by providing lower supply voltages for noncritical blocks under the performance constraint. However, the resulted lower voltage drop noise margin brings serious obstacles in power/ground (P/G) network design of the wire-bonding package. For voltage drop optimization, both block and power pad positions are important factors that need to be considered. Traditional multi-voltage floorplanning methods use rough estimation to evaluate the P/G network resource without considering the locations of power pads. To remedy this deficiency, in this paper, an efficient voltage drops aware power pad assignment (PPA) method is proposed, and it is further integrated into a floorplanning algorithm. We first present a fast PPA method for each power domain by the spring model. Then, to evaluate voltage drops during floorplanning iterations, the weighted distance from the blocks to the power pads is adopted as an optimization objective instead of time-consuming matrix computation. Experimental results on Gigascale System Research Center (GSRC) benchmark circuits indicate that the proposed method generates an optimized placement of power pads and floorplanning of blocks with high efficiency.decoupling capacitors configuration to alleviate the power delivery noise [12,13]. However, those techniques are implemented only when the floorplan or placement is ready. With exploding design complexity, it is necessary to consider voltage drop issues in the early design cycle [14][15][16][17]. Once the voltage drops aware floorplan is obtained, the detailed P/G network design can be performed in the subsequent placement and routing stages that consider Steiner tree construction and electromigration issues [18,19].It is reported that 5% of voltage decrease may cause the circuit performance slowdown up to 15% or more [20]. Hence, designers typically limit the voltage drops within 10% of the supply voltage to guarantee faultless operation [21]. Lower supply voltage indicates that lower noise margins or smaller voltage drops are permitted on the P/G network [22]. For instance, 1.5-V supply voltages permit 150-mV voltage drop while 1.0-V supply voltages only allow 100-mV voltage drop. Compared with single-voltage SoC, the voltage drop constraints present more challenges for the P/G network design of the multi-voltage SoC. First, from a low-power perspective, a VI with a larger area and a lower supply voltage is preferred during the VI generation process. However, the permitted ultra-low voltage drops make the P/G network hard to design. Second, power pads are located at the periphery of the chip for wire-bonding package. Locations of power pads affect both the timing and voltage drops [23]. Although multiple power pads for each VI can leverage the voltage drops, it may not be practical because the power pads must compete with other signal I/Os under the limited pad resource. Thus, it is vital to consider voltage drops in P/G network design for multi-voltage SoC. Related workConsid...