Symmetrical buffered clock-tree synthesis with supply-voltage alignment

Shih, Xin-Wei; Hsu, Tzu-Hsuan; Lee, Hsu-Chieh; Chang, Yao-Wen; Chao, Kai-Yuan

doi:10.1109/aspdac.2013.6509637

Cited by 2 publications

(1 citation statement)

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“…Moreover, temperature changes whenever activity changes and thus it is extremely difficult to alter the design structurally to cover every possible scenario. Similar case happens in the work proposed by researcher [31], in which clock trees are synthesized based on supply voltage drop profile. Clock buffer is one of the main factors of voltage drop.…”

Section: Introductionmentioning

confidence: 64%

Practical Full Chip Clock Distribution Design With a Flexible Topology and Hybrid Metaheuristic Technique

et al. 2021

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This paper recommends a practical technique to design full chip (FC) clock tree of a complex system-on-chip (SoC). In the new business environment, the market prefers a highly integrated but low power SoC with fast design productivity and low development cost. We observed that many techniques proposed in the prior arts are no longer practical or enough. With that, we introduce a flexible FC Clock network topology and a synthesis algorithm that utilize a hybrid meta-heuristic technique to search for near optimum solution in shorter turn-around time. Our work on a 10nm SoC product showed that the topology and algorithm managed to produce averagely 16.98% better global skew, 42.75% less divergence on critical clock paths and with 64.5% shorter clock balancing phase compared to a conventional ASIC methodology.INDEX TERMS system-on-a-chip (SoC), clock distribution, deep sub-micrometer, artificial intelligence, hybrid meta-heuristic.

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Section: Introductionmentioning

confidence: 64%