Symbolic layout for rapid full-custom prototyping of high-speed telecommunications chips

Boyer, D.G.; Cordell, R.R.

doi:10.1109/hicss.1989.47147

Cited by 10 publications

(1 citation statement)

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“…Such flexibility is vital in an environment where a wide range of design methods and technologies are used. Rink has been used to analyze chips ranging from Gallium Arsenide laser drivers to bipolar lightwave amplifiers to CMOS VLSI signal processors [ 5 ] , [9], [IO]. The shorrfrnder utility is a recent enhancement to the Rink system that solves the difficult problem of locating shorts between complex nets.…”

Section: Overview Of Shortfindermentioning

confidence: 99%

SHORTFINDER: a graphical CAD tool for locating net-to-net shorts in VLSI chip layouts

Gannett¹

1990

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Despite advances in CAD tools, layout errors resulting in electrical shorts between complex nets continue to cause trouble in many VLSI design projects. Locating the geometrical features causing shorts is often the most vexing problem faced during the layout verification process. Although this problem is common and important, there seems to be no published literature dealing with short location. This paper describes a new interactive CAD tool, called shortfinder, that enables the user to find such errors quickly and with minimal effort. This is accomplished by displaying a cycle-free shortest electrical path between two points indicated by the user on a graphical display of the layout. Shorrfinder was implemented as a modular enhancement to an existing layout viewing program: its data structures and algorithms are described in this paper.

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Section: Overview Of Shortfindermentioning

confidence: 99%